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參數(shù)資料
| 型號(hào)： | ATF22V10C-7XC |
| 廠商： | Atmel |
| 文件頁數(shù)： | 20/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD 7NS 24TSSOP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 系列： | 22V10 |
| 可編程類型： | EE PLD |
| 宏單元數(shù)： | 10 |
| 輸入電壓： | 5V |
| 速度： | 7ns |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | ATF22V10C7XC |
7
0735U–PLD–7/10
Atmel ATF22V10C(Q)
4.7
Power-up Reset
The registers in the Atmel ATF22V10Cs are designed to reset during power-up. At a point delayed slightly from
V
CC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the
output buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how V
CC actually rises in the system, the following conditions are required:
1.
The V
CC rise must be monotonic, and starts below 0.7V
2.
After reset occurs, all input and feedback setup times must be met before driving the clock pin high
3.
The clock must remain stable during t
PR
Figure 4-1.
Power-up Reset Timing
4.8
Preload of Registered Outputs
The ATF22V10C registers are provided with circuitry to allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by most of the approved programmers after the programming.
5.
Electronic Signature Word
There are 64-bits of programmable memory that are always available to the user, even if the device is secured.
These bits can be used for user-specific data.
6.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF22V10C fuse patterns. Once programmed,
fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible.
The security fuse should be programmed last, as its effect is immediate.
7.
Programming/Erasing
Programming/erasing is performed using standard PLD programmers. See “CMOS PLD Programming Hardware
and Software Support” for information on software/programming.
Table 7-1.
Programming/Erasing
C
LOCK
VRST
POWER
REGISTERED
OUTPUTS
tS
t PR
t W
Parameter
Description
Typ
Max
Units
t
PR
Power-up Reset Time
600
1,000
ns
V
RST
Power-up Reset Voltage
3.8
4.5
V
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