
5
0250M–PLD–7/10
Atmel ATF22V10B
6.
Input Test Waveforms and Measurement Levels
t
R,tF < 3ns
7.
Output Test Loads
* All except -7 which is R2 = 300
8.
Pin Capacitance
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested
9.
Power-up Reset
The registers in the Atmel ATF22V10B are designed to reset during power-up. At a point delayed slightly from
V
CC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the out-
put buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how V
CC actually rises in the system, the following conditions are required:
1. The V
CC rise must be monotonic
2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high
3. The clock must remain stable during t
PR
Commercial
Military
Typ
Max
Units
Conditions
C
IN
5
8
pF
V
IN =0V
C
OUT
6
8
pF
V
OUT =0V