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參數(shù)資料
| 型號： | ATF22LV10CZ-25JC |
| 廠商： | Atmel |
| 文件頁數(shù)： | 16/19頁 |
| 文件大小： | 0K |
| 描述： | IC PLD 25NS 28PLCC |
| 標準包裝： | 38 |
| 系列： | 22V10 |
| 可編程類型： | EE PLD |
| 宏單元數(shù)： | 10 |
| 輸入電壓： | 3.3V |
| 速度： | 25ns |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 管件 |
| 其它名稱： | ATF22LV10CZ25JC |
6
0779M–PLD–7/10
Atmel ATF22LV10C(Q)Z
4.4
Input Test Waveforms
4.4.1
Input Test Waveforms and Measurement Levels
4.4.2
Output Test Loads
Note:
Similar competitors devices are specified with slightly different loads. These load differences may affect output signals’
delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible device specification
conditions
4.5
Pin Capacitance
Table 4-1.
Pin Capacitance (f = 1MHz,T=25
C(1))
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested
4.6
Power-up Reset
The registers in the Atmel ATF22LV10CZ/CQZ are designed to reset during power-up. At a point delayed slightly
from V
CC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the
buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how V
CC actually rises in the system, the following conditions are required:
1.
The V
CC rise must be monotonic and start below 0.7V
2.
The clock must remain stable during T
PR
3.
After T
PR, all input and feedback setup times must be met before driving the clock pin high
4.7
Preload of Register Outputs
The ATF22LV10CZ/CQZ’s registers are provided with circuitry to allow loading of each register with either a high or
a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by most of the approved programmers after the programming.
Typ
Max
Units
Conditions
C
IN
5
8
pF
V
IN =0V
C
I/O
6
8
pF
V
OUT =0V
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相關代理商/技術參數(shù) |
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|---|---|
| ATF22LV10CZ-25JI | 功能描述:SPLD - 簡單可編程邏輯器件 EEPLD 500GATE 3.3V 5V PWR 25NS IND TEMP RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| ATF22LV10CZ-25PC | 功能描述:SPLD - 簡單可編程邏輯器件 500 GATE 3.3V-5V SPLY ZERO PWR-25NS RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| ATF22LV10CZ-25PI | 功能描述:SPLD - 簡單可編程邏輯器件 EEPLD 500GATE 3.3V 5V PWR 25NS IND TEMP RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| ATF22LV10CZ-25SC | 功能描述:SPLD - 簡單可編程邏輯器件 500 GATE 3.3V-5V SPLY ZERO PWR-25NS RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| ATF22LV10CZ-25SI | 功能描述:SPLD - 簡單可編程邏輯器件 EEPLD 500GATE 3.3V 5V PWR 25NS IND TEMP RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
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