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參數(shù)資料
| 型號： | ATF1516AS-15QHC208 |
| 廠商： | ATMEL CORP |
| 元件分類： | PLD |
| 英文描述： | High Performance EE-Based CPLD |
| 中文描述： | EE PLD, 15 ns, PQFP208 |
| 封裝： | HEAT SPREADER, PLASTIC, RQFP-208 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 266K |
| 代理商： | ATF1516AS-15QHC208 |
1
High
Performance
EE-Based CPLD
ATF1516AS/L
Preliminary
Features
High Density, High Performance Electrically Erasable Complex
Programmable Logic Device
– 256 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 160, 192, 208-pins
– 10 ns Maximum Pin-to-Pin Delay
– Registered Operation Up To 100 MHz
– Enhanced Routing Resources
Flexible Logic Macrocell
– D/T/Latch Configurable Flip Flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic utilization by burying a register within a COM output
Advanced Power Management Features
– Automatic 3 mA Stand-By for “L” Version (Max.)
– Pin-Controlled 4 mA Stand-By Mode (Typical)
– Programmable Pin-Keeper Inputs and I/Os
– Reduced-Power Feature Per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 160-pin PQFP, 192 PGA and 208-pin RQFP Packages
Advanced EE Technology
– 100% Tested
– Completely Reprogrammable
– 100 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-Up Immunity
JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
Fast In-System Programmability (ISP) via JTAG
PCI-compliant
3.3 or 5.0V I/O pins
Security Fuse Feature
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
D - Latch Mode
Combinatorial Output with Registered Feedback within any Macrocell
Three Global Clock Pins
ITD ( Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-Keeper” Option
V
Power-Up Reset Option
Pull-Up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
– Edge Controlled Power Down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
Rev. 0994A-A–01/98
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PDF描述 |
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| ATF1516ASL-25QHC208 | High Performance EE-Based CPLD |
| ATF1516AS-15QHI208 | High Performance EE-Based CPLD |
| ATF1516ASL-25QHI208 | High Performance EE-Based CPLD |
| ATF1516ASL-25QI60 | High Performance EE-Based CPLD |
| ATF1516AE-5 | 2nd Generation EE Complex Programmable Logic Devices |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATF1516AS-15QHI208 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance EE-Based CPLD |
| ATF1516AS-15QI160 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| ATF1516AS-15UC192 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance EE-Based CPLD |
| ATF1516AS-15UI192 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance EE-Based CPLD |
| ATF1516ASL | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance EE-Based CPLD |
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