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參數(shù)資料
| 型號： | ATF1508ASZ-25QC160 |
| 廠商： | ATMEL CORP |
| 元件分類： | PLD |
| 英文描述： | High Performance E2 PLD |
| 中文描述： | EE PLD, 25 ns, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 1/22頁 |
| 文件大?。?/td> | 519K |
| 代理商： | ATF1508ASZ-25QC160 |
1
High-
performance
EE PLD
ATF1508ASV
ATF1508ASVL
Features
High-density, High-performance, Electrically-erasable
Complex Programmable Logic Device
– 3.0V to 3.6V Operating Range
– 128 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 84, 100, 160 Pins
– 15 ns Maximum Pin-to-pin Delay
– Registered Operation up to 77 MHz
– Enhanced Routing Resources
Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register within a COM Output
Advanced Power Management Features
– Automatic 5 μA Standby for “L” Version
– Pin-controlled 100 μA Standby Mode
– Programmable Pin-keeper Inputs and I/Os
– Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 84-lead PLCC and 100-lead PQFP and TQFP and
160-lead PQFP Packages
Advanced EE Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
Fast In-System Programmability (ISP) via JTAG
PCI-compliant
Security Fuse Feature
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Transparent-latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
V
CC
Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts
Rev. 1408E–09/00
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATF1508ASZ-25QI100 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance E2 PLD |
| ATF1508ASZ-25QI160 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance E2 PLD |
| ATF1508BE | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Highperformance CPLD |
| ATF1508BE-5AX100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 128MV CPLD, 1.8V 100-pin RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508BE-5CX132 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Highperformance CPLD |
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