參數(shù)資料
型號: ATF1508ASVL-20QI160
廠商: Atmel
文件頁數(shù): 6/28頁
文件大?。?/td> 0K
描述: IC PLD EE VLOW PWR 20NS 160-PQFP
標準包裝: 24
系列: ATF15xx
可編程類型: 系統(tǒng)內可編程(最少 10,000 次編程/擦除循環(huán))
最大延遲時間 tpd(1): 20.0ns
電壓電源 - 內部: 3 V ~ 3.6 V
宏單元數(shù): 128
輸入/輸出數(shù): 96
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 160-BQFP
供應商設備封裝: 160-PQFP(28x28)
包裝: 托盤
其它名稱: ATF1508ASV20QI160
14
ATF1508ASV(L)
1408H–PLD–7/05
Output AC Test Loads
Power-down Mode
The ATF1508ASV(L) includes two pins for optional pin-controlled power-down feature.
When this mode is enabled, the PD pin acts as the power-down pin. When the PD1 and
PD2 pin is high, the device supply current is reduced to less than 5 mA. During power-
down, all output data and internal logic states are latched and held. Therefore, all regis-
tered and combinatorial output data remain valid. Any outputs that were in a high-Z state
at the onset will remain at high-Z. During power-down, all input signals except the
power-down pin are blocked. Input and I/O hold latches remain active to ensure that
pins do not float to indeterminate levels, further reducing system power. The power-
down pin feature is enabled in the logic design file. Designs using either power-down pin
may not use the PD pin logic array input. However, buried logic resources in this macro-
cell may still be used.
Notes:
1. For slow slew outputs, add t
SSO.
2. Pin or product term.
3.0V
703
8060
Power Down AC Characteristics(1)(2)
Symbol
Parameter
-15
-20
Units
Min
Max
Min
Max
t
IVDH
Valid I, I/O before PD High
15
20
ns
tGVDH
Valid OE(2) before PD High
15
20
ns
tCVDH
Valid Clock(2) before PD High
15
20
ns
t
DHIX
I, I/O Don’t Care after PD High
25
30
ns
tDHGX
OE(2) Don’t Care after PD High
25
30
ns
t
DHCX
Clock(2) Don’t Care after PD High
25
30
ns
t
DLIV
PD Low to Valid I, I/O
1
s
tDLGV
PD Low to Valid OE (Pin or Term)
1
s
t
DLCV
PD Low to Valid Clock (Pin or Term)
1
s
t
DLOV
PD Low to Valid Output
1
s
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