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參數(shù)資料
| 型號： | ATF1508ASVL-20QI100 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 25/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD EE VLOW PWR 20NS 100-PQFP |
| 標準包裝： | 66 |
| 系列： | ATF15xx |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時間 tpd(1)： | 20.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 宏單元數(shù)： | 128 |
| 輸入/輸出數(shù)： | 80 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-PQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | ATF1508ASV20QI100 |
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ATF1508ASV(L)
1408H–PLD–7/05
Extra Feedback
The ATF15xxSE Family macrocell output can be selected as registered or combinato-
rial. The extra buried feedback signal can be either combinatorial or a registered signal
regardless of whether the output is combinatorial or registered. (This enhancement
function is automatically implemented by the fitter software.) Feedback of a buried com-
binatorial output allows the creation of a second latch within a macrocell.
I/O Control
The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be
individually configured as an input, output or for bi-directional operation. The output
enable for each macrocell can be selected from the true or compliment of the two output
enable pins, a subset of the I/O pins, or a subset of the I/O macrocells. This selection is
automatically done by the fitter software when the I/O is configured as an input, all mac-
rocell resources are still available, including the buried feedback, expander and cascade
logic.
Global Bus/Switch Matrix
The global bus contains all input and I/O pin signals as well as the buried feedback sig-
nal from all 128 macrocells. The switch matrix in each logic block receives as its inputs
all signals from the global bus. Under software control, up to 40 of these signals can be
selected as inputs to the logic block.
Foldback Bus
Each macrocell also generates a foldback product term. This signal goes to the regional
bus and is available to 16 macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The 16 foldback terms in each region allow generation of
high fan-in sum terms (up to 21 product terms) with little additional delay.
Open-collector Output Option
This option enables the device output to provide control signals such as an interrupt that
can be asserted by any of the several devices.
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參數(shù)描述 |
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| ATF1508ASVL-20QI160 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 128 MACROCELL 3.3V 20NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508ASZ | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance E2 PLD |
| ATF1508ASZ-20AC100 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance E2 PLD |
| ATF1508ASZ-20JC84 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance E2 PLD |
| ATF1508ASZ-20QC100 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance E2 PLD |
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