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參數(shù)資料
| 型號： | ATF1504ASV-15JC68 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 31/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 64 MACROCELL LV 68PLCC |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 系列： | ATF15xx |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時(shí)間 tpd(1)： | 15.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 宏單元數(shù)： | 64 |
| 輸入/輸出數(shù)： | 48 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC（24.23x24.23） |
| 包裝： | 管件 |
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9
ATF1504ASV(L)
1409J–PLD–6/05
All power-down AC characteristic parameters are computed from external input or I/O
pins, with reduced-power bit turned on. For macrocells in reduced-power mode
(reduced-power bit turned on), the reduced-power adder, t
RPA, must be added to the AC
parameters, which include the data paths t
LAD, tLAC, tIC, tACL, tACH and tSEXP.
The ATF1504ASV(L) macrocell also has an option whereby the power can be reduced
on a per macrocell basis. By enabling this power-down option, macrocells that are not
used in an application can be turned down, thereby reducing the overall power con-
sumption of the device.
Each output also has individual slew rate control. This may be used to reduce system
noise by slowing down outputs that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast switching in the design file.
Design Software
Support
ATF1504ASV(L) designs are supported by several industry standard third party tools.
Automated fitters allow logic synthesis using a variety of high-level description lan-
guages and formats.
Power-up Reset
The ATF1504ASV is designed with a power-up reset, a feature critical for state machine
initialization. At a point delayed slightly from V
CC crossing VRST, all registers will be ini-
tialized, and the state of each output will depend on the polarity of its buffer. However,
due to the asynchronous nature of reset and uncertainty of how V
CC actually rises in the
system, the following conditions are required:
1.
The V
CC rise must be monotonic,
2.
After reset occurs, all input and feedback setup times must be met before driving
the clock pin high, and,
3.
The clock must remain stable during T
D.
The ATF1504ASV has two options for the hysteresis about the reset level, V
RST, Small
and Large. To ensure a robust operating environment in applications where the device
is operated near 3.0V, Atmel recommends that during the fitting process users configure
the device with the Power-up Reset hysteresis set to Large. For conversions, Atmel
POF2JED users should include the flag “-power_reset” on the command line after “file-
name.POF”. To allow the registers to be properly reinitialized with the Large hysteresis
option selected, the following condition is added:
4.
If V
CC falls below 2.0V, it must shut off completely before the device is turned on
again.
When the Large hysteresis option is active, I
CC is reduced by several hundred micro-
amps as well.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF1504ASV(L) fuse
patterns. Once programmed, fuse verify is inhibited. However, the 16-bit User Signature
remains accessible.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATF1504ASV-15JC84 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 64 MACROCELL w/ISP STD PWR 3.3V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1504ASV-15JI44 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 64 MACROCELL w/ISP STD PWR 3.3V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1504ASV-15JI68 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 ASICS RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1504ASV-15JI84 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 64 MACROCELL 3.3V 15NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1504ASV-15JU44 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 64 MACROCELL w/ISP STD PWR 3.3V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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