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參數(shù)資料
| 型號(hào)： | ATF1502ASV-15AU44 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 21/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD EE HP 15NS 44-TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | ATF15xx |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時(shí)間 tpd(1)： | 15.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 宏單元數(shù)： | 32 |
| 輸入/輸出數(shù)： | 32 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-TQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 608 (CN2011-ZH PDF) |
| 配用： | ATF15XX-DK3-ND - KIT DEV FOR ATF15XX CPLD'S |
5
1615J–PLD–01/06
ATF1502ASV
1.3
Flip-flop
The ATF1502ASV’s flip-flop has very flexible data and control functions. The data input can
come from either the XOR gate, from a separate product term or directly from the I/O pin. Select-
ing the separate product term allows creation of a buried registered feedback within a
combinatorial output macrocell. (This feature is automatically implemented by the fitter soft-
ware). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-
through latch. In this mode, data passes through when the clock is high and is latched when the
clock is low.
The clock itself can be either one of the Global CLK signals (GCK[0 : 2]) or an individual product
term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the
clock, one of the macrocell product terms can be selected as a clock enable. When the clock
enable function is active and the enable signal (product term) is low, all clock edges are ignored.
The flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a prod-
uct term, or always off. AR can also be a logic OR of GCLEAR with a product term. The
asynchronous preset (AP) can be a product term or always off.
1.4
Extra Feedback
The ATF1502ASV macrocell output can be selected as registered or combinatorial.The extra
buried feedback signal can be either combinatorial or a registered signal regardless of whether
the output is combinatorial or registered. (This enhancement function is automatically imple-
mented by the fitter software.) Feedback of a buried combinatorial output allows the creation of a
second latch within a macrocell.
1.5
I/O Control
The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be individ-
ually configured as an input, output or for bi-directional operation. The output enable for each
macrocell can be selected from the true or compliment of the two output enable pins, a subset of
the I/O pins, or a subset of the I/O macrocells. This selection is automatically done by the fitter
software when the I/O is configured as an input, all macrocell resources are still available,
including the buried feedback, expander and cascade logic.
1.6
Global Bus/Switch Matrix
The global bus contains all input and I/O pin signals as well as the buried feedback signal from
all 32 macrocells. The switch matrix in each logic block receives as its inputs all signals from the
global bus. Under software control, up to 40 of these signals can be selected as inputs to the
logic block.
1.7
Foldback Bus
Each macrocell also generates a foldback product term. This signal goes to the regional bus and
is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s prod-
uct terms. The four foldback terms in each region allow generation of high fan-in sum terms (up
to nine product terms) with little additional delay.
2.
Programmable Pin-keeper Option for Inputs and I/Os
The ATF1502ASV offers the option of programming all input and I/O pins so that pin-keeper cir-
cuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will
stay at that previous high or low level. This circuitry prevents unused input and I/O lines from
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| ATF1502ASV-15JC44 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 32 MACROCELL ISP STD PWR 3.3V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1502ASV-15JI44 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 32 MACROCELL ISP STD PWR 3.3V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1502ASV-15JU44 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 32 MACROCELL ISP STD PWR 3.3V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1502ASV-20AC44 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 32 MACROCELL ISP STD PWR 3.3V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1502ASV-20AI44 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 32 MACROCELL ISP STD PWR 3.3V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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