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參數(shù)資料
| 型號： | ATA6620-TASY |
| 廠商： | Atmel |
| 文件頁數(shù)： | 16/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX LIN BUS 5V/50MA 8SOIC |
| 標準包裝： | 112 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | LIN |
| 電源電壓： | 5 V ~ 18 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 管件 |
3
4850I–AUTO–09/09
ATA6620N
3.
Functional Description
3.1
Physical Layer Compatibility
Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer),
all nodes with a LIN physical layer according to revision 2.0 can be mixed with LIN physical layer
nodes, which, according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), are without
any restrictions.
3.2
Supply Pin (VS)
LIN operating voltage is V
S = 5V to 18V. After switching on VS, the IC starts with the Pre-normal
mode and the voltage regulator is switched on (that is, 5V/50 mA output capability).
The supply current in Sleep mode is typically 10 A and 40 A in Silent mode.
3.3
Ground Pin (GND)
The IC is neutral on the LIN pin in case of GND disconnection. It is able to handle a ground shift
up to 3V for supply voltage above 9V at the VS pin.
3.4
Voltage Regulator Output Pin (VCC)
The internal 5V voltage regulator is capable of driving loads with up to 50 mA, supplying the
microcontroller and other ICs on the PCB. It is protected against overload by means of current
limitation and overtemperature shut-down. Furthermore, the output voltage is monitored and will
cause a reset signal at the NRES output pin if it drops below a defined threshold V
thun.
3.5
Undervoltage Reset Output (NRES)
This push-pull output is supplied from the V
CC voltage. If the VCC voltage falls below the under-
voltage detection threshold of V
thun, NRES switches to low after tres_f (see Figure 4-7 on page
11) except the IC is switched into Sleep mode. Even if V
CC = 0V the NRES stays low, because it
is internally driven from the V
S voltage. If VS voltage ramps down, NRES stays low until
V
S < 1.5V and then becomes highly resistive.
The implemented undervoltage delay keeps NRES low for t
Reset =10ms after VCC reaches its
nominal value.
3.6
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown, as well as an internal
pull-up resistor according to LIN specification 2.0 is implemented. The voltage range is from
–40V to +60V. This pin exhibits no reverse current from the LIN bus to V
S, even in the case of a
GND shift or V
Batt disconnection. The LIN receiver thresholds are compatible with the LIN proto-
col specification.
The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are
slope controlled. The output has a short-circuit limitation. This is a self-adapting current limita-
tion; that is, during current limitation, as the chip temperature increases, the current decreases.
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