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參數(shù)資料
| 型號(hào)： | ATA010A0X43Z |
| 廠商： | LINEAGE POWER LLC |
| 元件分類： | 電源模塊 |
| 英文描述： | 1-OUTPUT DC-DC REG PWR SUPPLY MODULE |
| 封裝： | ROHS COMPLIANT, SIP-10 |
| 文件頁(yè)數(shù)： | 2/19頁(yè) |
| 文件大?。?/td> | 686K |
| 代理商： | ATA010A0X43Z |
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Data Sheet
October 1, 2009
Austin LynxTM II 12V SIP Non-isolated Power Modules:
8.3 – 14Vdc input; 0.75Vdc to 5.5Vdc Output; 10A output current
LINEAGE POWER
10
Test Configurations
TO OSCILLOSCOPE
CURRENT PROBE
LTEST
1μH
B
A
TTE
R
Y
CS 1000μF
Electrolytic
E.S.R.<0.1
Ω
@ 20°C 100kHz
2x100μF
Tantalum
VIN(+)
COM
NOTE: Measure input reflected ripple current with a simulated
source inductance (LTEST) of 1μH. Capacitor CS offsets
possible battery impedance. Measure current as shown
above.
CIN
Figure 23. Input Reflected Ripple Current Test
Setup.
NOTE: All voltage measurements to be taken at the module
terminals, as shown above. If sockets are used then
Kelvin connections are required at the module terminals
to avoid measurement errors due to socket contact
resistance.
VO(+)
COM
1uF .
RESISTIVE
LOAD
SCOPE
COPPER STRIP
GROUND PLANE
10uF
Figure 24. Output Ripple and Noise Test Setup.
VO
COM
VIN(+)
COM
RLOAD
Rcontact
Rdistribution
Rcontact
Rdistribution
Rcontact
Rdistribution
VIN
VO
NOTE: All voltage measurements to be taken at the module
terminals, as shown above. If sockets are used then
Kelvin connections are required at the module terminals
to avoid measurement errors due to socket contact
resistance.
Figure 25. Output Voltage and Efficiency Test Setup.
η =
VO. IO
VIN. IIN
x 100 %
Efficiency
Design Considerations
Input Filtering
Austin Lynx
TM II SIP module should be connected to a
low-impedance source. A highly inductive source can
affect the stability of the module. An input capacitance
must be placed directly adjacent to the input pin of the
module, to minimize input ripple voltage and ensure
module stability.
In a typical application, 4x47 F low-ESR tantalum
capacitors (AVX part #: TPSE476M025R0100, 47F
25V 100 m ESR tantalum capacitor) will be sufficient
to provide adequate ripple voltage at the input of the
module. To minimize ripple voltage at the input, low
ESR ceramic capacitors are recommended at the input
of the module. Figure 26 shows input ripple voltage
(mVp-p) for various outputs with 4x47 F tantalum
capacitors and with 4x22 F ceramic capacitor (TDK
part #: C4532X5R1C226M) at full load.
Input
R
ippl
e
Vol
tage
(mVp-
p
)
0
50
100
150
200
250
300
0
1
2
3456
Tantalum
Ceramic
Output Voltage (Vdc)
Figure 26. Input ripple voltage for various output
with 4x47 F tantalum capacitors and with 4x22 F
ceramic capacitors at the input (full load).
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