參數(shù)資料
型號: AT93C56A-10PI-1.8
廠商: ATMEL CORP
元件分類: PROM
英文描述: 3-wire Serial EEPROMs 2K (256 x 8 or 128 x 16)
中文描述: 128 X 16 MICROWIRE BUS SERIAL EEPROM, PDIP8
封裝: 0.300 INCH, PLASTIC, MS-001BA, DIP-8
文件頁數(shù): 14/17頁
文件大小: 277K
代理商: AT93C56A-10PI-1.8
6
AT93C56A/66A [Preliminary]
3378H–SEEPR–8/05
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle t
WP starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of
250 ns (t
CS). A logic “0” at DO indicates that programming is still in progress. A logic “1”
indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
READY/BUSY status cannot be obtained if the CS is brought high after the end of
the self-timed programming cycle t
WP.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-
ory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns (t
CS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy
status of the part if CS is brought high after being kept low for a minimum of 250 ns (t
CS).
The WRAL instruction is valid only at V
CC = 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the READ instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
Timing Diagrams
Figure 2. Synchronous Data Timing
Note:
1. This is the minimum SK period.
相關(guān)PDF資料
PDF描述
AT93C56A 3-wire Serial EEPROMs 2K (256 x 8 or 128 x 16)
ATE2DGPC1 TOGGLE SWITCH, DPDT, LATCHED, THROUGH HOLE-STRAIGHT
ATFC-0201-8N2-J-T 1 ELEMENT, 0.0082 uH, CERAMIC-CORE, GENERAL PURPOSE INDUCTOR, SMD
ATFC-0201-5N6-G-T 1 ELEMENT, 0.0056 uH, CERAMIC-CORE, GENERAL PURPOSE INDUCTOR, SMD
ATFC-0201-10N-J-T 1 ELEMENT, 0.01 uH, CERAMIC-CORE, GENERAL PURPOSE INDUCTOR, SMD
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