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參數(shù)資料
| 型號： | AT91SAM9N12-EK |
| 廠商： | Atmel |
| 文件頁數(shù)： | 11/27頁 |
| 文件大小： | 0K |
| 描述： | EVAL KIT FOR SAM9N12 |
| 設(shè)計(jì)資源： | AT91SAM9N12-EK Design & Mfg Files SAM9N12-EK Design & Mfg File Information |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ATSAM9N12 |
| 所含物品： | 板 |
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11096AS–ATARM–4-Oct-11
SAM9N12
6.3
External Memories Overview
The SAM9N12 features a External Bus Interface to offer interface to a wide range of external
memories and to any parallel peripheral.
6.3.1
External Bus Interface
Integrates three External Memory Controllers:
– Static Memory Controller
– DDR2/SDRAM Controller
– MLC NAND Flash ECC Controller
Up to 26-bit Address Bus (up to 64MBytes linear per chip select)
Up to 6 chips selects, Configurable Assignment:
– Static Memory Controller on NCS0, NCS1, NCS2, NCS3, NCS4, NCS5
– DDR2/SDRAM Controller (SDCS) or Static Memory Controller on NCS1
– NAND Flash support on NCS3
6.3.2
Static Memory Controller
8- or 16-bit Data Bus
Multiple Access Modes supported
– Byte Write or Byte Select Lines
– Asynchronous read in Page Mode supported (4- up to 16-byte page size)
Multiple device adaptability
– Control signals programmable setup, pulse and hold time for each Memory Bank
Multiple Wait State Management
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
Slow Clock mode supported
6.3.3
DDR-SDRAM Controller
Supports DDR2-SDRAM, Low-power DDR1-SDRAM or DDR2-SDRAM, SDR-SDRAM and
Low-power SDR-SDRAM
Numerous Configurations Supported
– 2K, 4K, 8K, 16K Row Address Memory Parts
– SDRAM with 4 Internal Banks
– SDR-SDRAM with 16-bit or 32-bit Data Path
– DDR-SDRAM with 16-bit Data Path
– One Chip Select for SDRAM Device (256 Mbytes Address Space)
Programming Facilities
– Multibank Ping-pong Access (Up to 4 Banks or 8 Banks Opened at Same Time =
Reduced Average Latency of Transactions)
– Timing Parameters Specified by Software
– Automatic Refresh Operation, Refresh Rate is Programmable
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