參數(shù)資料
型號(hào)： AT91SAM9G10-CU
廠商： Atmel
文件頁(yè)數(shù)： 19/39頁(yè)
文件大?。?/td> 0K
描述： IC MCU ARM9 SAMPLING 217CBGA
產(chǎn)品培訓(xùn)模塊： MCU Product Line Introduction
標(biāo)準(zhǔn)包裝： 126
系列： SAM9G
核心處理器： ARM9
芯體尺寸： 16/32-位
速度： 266MHz
連通性： EBI/EMI，I²C，IrDA，ISI，MMC，SPI，SSC，UART/USART，USB
外圍設(shè)備： DMA，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 96
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類(lèi)型： ROM
RAM 容量： 48K x 8
電壓 - 電源 (Vcc/Vdd)： 1.08 V ~ 1.32 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 217-LFBGA
包裝： 托盤(pán)
26
6462AS–ATARM–03-Jun-09
AT91SAM9G10
10.3
Peripheral Multiplexing on PIO Lines
The AT91SAM9G10 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O
lines of the peripheral set.
Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two
page 30 define how the I/O lines of the peripherals A and B are multiplexed on the PIO Control-
lers. The two columns “Function” and “Comments” have been inserted for the user’s own
comments; they may be used to track how pins are defined in an application.
Note that some output only peripheral functions might be duplicated within the tables.
The column “Reset State” indicates whether the PIO line resets in I/O mode or in peripheral
mode. If I/O is mentioned, the PIO line resets in input with the pull-up enabled, so that the device
is maintained in a static state as soon as the reset is released. As a result, the bit corresponding
to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO line is assigned to this func-
tion and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling
memories, in particular the address lines, which require the pin to be driven as soon as the reset
is released. Note that the pull-up resistor is also enabled in this case.
10.3.1
Resource Multiplexing
10.3.1.1
LCD Controller
The LCD Controller can interface with several LCD panels. It supports 4, 8 or 16 bit-per-pixel
without any limitation. Interfacing 24 bit-per-pixel TFTs panel prevents using the SSC0 and the
chip select line 0 of the SPI1.
16 bit-per-pixel TFT panels are interfaced through peripheral B functions, as color data is output
on LCDD3 to LCDD7, LCDD11 to LCDD15 and LCDD19 to LCDD23. Intensity bit is output on
LCDD2, LCDD10 and LCDD18. Using the peripheral B does not prevent using the SSC0 and
the SPI1 lines.
10.3.1.2
EBI
If not required, the NWAIT function (external wait request) can be deactivated by software,
allowing this pin to be used as a PIO.
10.3.1.3
32-bit Data Bus
Using a 32-bit Data Bus prevents:
using the three Timer Counter channels’ outputs and trigger inputs
using the SSC2
10.3.1.4
NAND Flash Interface
Using the NAND Flash interface prevents:
using NCS3, NCS6 and NCS7 to access other parallel devices
10.3.1.5
Compact Flash Interface
Using the CompactFlash interface prevents:
using NCS4 and/or NCS5 to access other parallel devices
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