參數(shù)資料
型號: AT91SAM9261B-CU-999
廠商: Atmel
文件頁數(shù): 4/44頁
文件大小: 0K
描述: IC MCU ARM9 ULT LOW PWR 217LFBGA
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 500
系列: AT91SAM
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 190MHz
連通性: EBI/EMI,I²C,MMC,SPI,SSC,UART/USART,USB
外圍設(shè)備: DMA,LCD,POR,PWM,WDT
輸入/輸出數(shù): 96
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: ROM
RAM 容量: 192K x 8
電壓 - 電源 (Vcc/Vdd): 1.08 V ~ 1.32 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 217-LFBGA
包裝: 帶卷 (TR)
12
6062LS–ATARM–23-Mar-09
AT91SAM9261
6.2
Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a perma-
nent pull-down resistor of about 15 k
Ω to GNDBU, so that it can be left unconnected for normal
operations. Driving this line at a high level leads to unpredictable results.
6.3
Reset Pin
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven
with voltage at up to VDDIOP. As the product integrates power-on reset cells, the NRST pin can
be left unconnected in case no reset from the system needs to be applied to the product.
The NRST pin integrates a permanent pull-up resistor of 100 k
Ω minimum to VDDIOP.
The NRST signal is inserted in the Boundary Scan.
6.4
PIO Controller A, B and C Lines
All the I/O lines PA0 to PA31, PB0 to PB31, and PC0 to PC31 integrate a programmable pull-up
resistor of 100 k
Ω. Programming of this pull-up resistor is performed independently for each I/O
line through the PIO Controllers.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which
are multiplexed with the External Bus Interface signals that require to be enabled as Peripherals
at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing
tables.
6.5
Shutdown Logic Pins
The SHDN pin is an output only, driven by Shutdown Controller.
The pin WKUP is an input only. It can accept voltages only between 0V and VDDBU.
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