參數(shù)資料
型號(hào)： AT91SAM9260B-CU
廠商： Atmel
文件頁(yè)數(shù)： 5/45頁(yè)
文件大?。?/td> 0K
描述： IC ARM9 MCU 217-LFBGA
產(chǎn)品培訓(xùn)模塊： SAM9 MPU Boot Solutions & Application Deployment
MCU Product Line Introduction
標(biāo)準(zhǔn)包裝： 126
系列： AT91SAM
核心處理器： ARM9
芯體尺寸： 16/32-位
速度： 180MHz
連通性： EBI/EMI，以太網(wǎng)，I²C，MMC，SPI，SSC，UART/USART，USB
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 96
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： ROM
RAM 容量： 24K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 217-LFBGA
包裝： 托盤
配用： AT91SAM9260-EK-ND - KIT EVAL FOR AT91SAM9260
AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
13
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
6.
I/O Line Considerations
6.1
JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors.
TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied to VDDBU). It integrates
a permanent pull-down resistor of about 15 k
Ω to GNDBU, so that it can be left unconnected for normal operations.
The NTRST signal is described in Section 6.3.
All the JTAG signals are supplied with VDDIOP0.
6.2
Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of
about 15 k
Ω to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to
unpredictable results.
This pin is supplied with VDDBU.
6.3
Reset Pins
NRST is a bidirectional with an open-drain output integrating a non-programmable pull-up resistor. It can be driven with
voltage at up to VDDIOP0.
NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the processor.
As the product integrates power-on reset cells, which manages the processor and the JTAG reset, the NRST and
NTRST pins can be left unconnected.
The NRST and NTRST pins both integrate a permanent pull-up resistor to VDDIOP0. Its value can be found in the table
“DC Characteristics” in the section “SAM9260 Electrical Characteristics” in the product datasheet.
The NRST signal is inserted in the Boundary Scan.
6.4
PIO Controllers
All the I/O lines managed by the PIO Controllers integrate a programmable pull-up resistor. Refer to the section on DC
Characteristics in “SAM9260 Electrical Characteristics” for more information. Programming of this pull-up resistor is
performed independently for each I/O line through the PIO Controllers.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the
External Bus Interface signals and that must be enabled as Peripheral at reset. This is explicitly indicated in the column
“Reset State” of the PIO Controller multiplexing tables.
6.5
I/O Line Drive Levels
The PIO lines are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently except PC4 to
PC31 that are VDDIOM powered.
6.6
Shutdown Logic Pins
The SHDN pin is a tri-state output pin, which is driven by the Shutdown Controller. There is no internal pull-up. An
external pull-up tied to VDDBU is needed and its value must be higher than 1 M
Ω. The resistor value is calculated
according to the regulator enable implementation and the SHDN level.
The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.
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