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參數(shù)資料
| 型號： | AT91SAM9260-EK |
| 廠商： | Atmel |
| 文件頁數(shù)： | 7/45頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL FOR AT91SAM9260 |
| 產(chǎn)品培訓模塊： | MCU Product Line Introduction |
| 標準包裝： | 1 |
| 系列： | AT91SAM 智能 ARM |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | AT91SAM9260 |
| 所含物品： | 評估板、并行纜線和光盤 |
| 相關(guān)產(chǎn)品： | AT91SAM9260B-CU-999-ND - IC MCU ARM9 217LFBGA AT91SAM9260B-QU-ND - IC ARM9 MCU 208-PQFP AT91SAM9260B-CU-ND - IC ARM9 MCU 217-LFBGA |
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15
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
7.
Processor and Architecture
7.1
ARM926EJ-S Processor
RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration
Two Instruction Sets
ARM High-performance 32-bit Instruction Set
Thumb High Code Density 16-bit Instruction Set
DSP Instruction Extensions
5-Stage Pipeline Architecture:
Instruction Fetch (F)
Instruction Decode (D)
Execute (E)
Data Memory (M)
Register Write (W)
8-Kbyte Data Cache, 8-Kbyte Instruction Cache
Virtually-addressed 4-way Associative Cache
Eight words per line
Write-through and Write-back Operation
Pseudo-random or Round-robin Replacement
Write Buffer
Main Write Buffer with 16-word Data Buffer and 4-address Buffer
DCache Write-back Buffer with 8-word Entries and a Single Address Entry
Software Control Drain
Standard ARM v4 and v5 Memory Management Unit (MMU)
Access Permission for Sections
Access Permission for large pages and small pages can be specified separately for each quarter of the
page
16 embedded domains
Bus Interface Unit (BIU)
Arbitrates and Schedules AHB Requests
Separate Masters for both instruction and data access providing complete Matrix system flexibility
Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface
On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)
7.2
Bus Matrix
6-layer Matrix, handling requests from 6 masters
Programmable Arbitration strategy
Fixed-priority Arbitration
Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master
Burst Management
Breaking with Slot Cycle Limit Support
Undefined Burst Length Support
One Address Decoder provided per Master
Three different slaves may be assigned to each decoded memory area: one for internal boot, one for
external boot, one after remap
相關(guān)PDF資料 |
PDF描述 |
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| 1331-271K | INDUCTOR SHIELDED 0.27UH SMD |
| 1331-222K | INDUCTOR SHIELDED 2.20UH SMD |
| 1331-221K | INDUCTOR SHIELDED 0.22UH SMD |
| 1331-182K | INDUCTOR SHIELDED 1.80UH SMD |
| 1331-181K | INDUCTOR SHIELDED 0.18UH SMD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT91SAM9260-QU | 功能描述:ARM微控制器 - MCU 2x4kB SRAM 180MHz - PWM RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| AT91SAM9261 | 制造商:Atmel Corporation 功能描述:ARM9 PROCESSOR W/LCD CONTROLLER - Bulk |
| AT91SAM9261_08 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb-based Microcontrollers |
| AT91SAM9261_09 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb-based Microcontrollers |
| AT91SAM9261_0903 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb-based Microcontrollers |
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