參數(shù)資料
型號: AT91SAM7X-EK
廠商: Atmel
文件頁數(shù): 5/44頁
文件大?。?/td> 0K
描述: KIT EVAL FOR AT91SAM7X256/128
產(chǎn)品培訓模塊: AT91SAM7X and SAM7XC Flash-based Microcontrollers
MCU Product Line Introduction
標準包裝: 1
系列: AT91SAM 智能 ARM
類型: MCU
適用于相關產(chǎn)品: AT91SAM7X256,AT91SAM7X128
所含物品: 板,線纜,DVD,電源
相關產(chǎn)品: AT91SAM7X256-CU-999-ND - IC MCU ARM7 256KB FLASH 100TFBGA
AT91SAM7X128-CU-999-ND - IC MCU ARM7 128KB FLASH 100TFBGA
AT91SAM7X128-AU-999-ND - IC MCU ARM7 128KB FLASH 100LQFP
AT91SAM7X512-CU-ND - MCU ARM 512K HS FLASH 100-TFBGA
AT91SAM7X512-AU-ND - MCU ARM 512K HS FLASH 100-LQFP
AT91SAM7X256-CU-ND - MCU ARM 256K HS FLASH 100-TFBGA
AT91SAM7X128-CU-ND - MCU ARM 128K HS FLASH 100-TFBGA
AT91SAM7X256-AU-999TR-ND - IC ARM7 MCU 256K FLASH 100-LQFP
AT91SAM7X256-AU-ND - IC ARM7 MCU FLASH 256K 100LQFP
AT91SAM7X128-AU-ND - IC ARM7 MCU FLASH 128K 100LQFP
13
6120GS–ATARM–07-Apr-11
SAM7X512/256/128 Summary
6.
I/O Lines Considerations
6.1
JTAG Port Pins
TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not
integrate a pull-up resistor.
TDO is an output, driven at up to VDDIO, and has no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The
JTAGSEL pin integrates a permanent pull-down resistor of about 15 k
Ω to GND.
To eliminate any risk of spuriously entering the JTAG boundary scan mode due to noise on
JTAGSEL, it should be tied externally to GND if boundary scan is not used, or pulled down with
an external low-value resistor (such as 1 k
Ω).
6.2
Test Pin
Th e T S T p i n is used f o r ma nu f a ct ur in g t e st o r f a st pr og ra mmi ng mod e of t h e
SAM7X512/256/128 when asserted high. The TST pin integrates a permanent pull-down resis-
tor of about 15 k
Ω to GND.
To eliminate any risk of entering the test mode due to noise on the TST pin, it should be tied to
GND if the FFPI is not used, or pulled down with an external low-value resistor (such as 1 k
Ω)
To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high
and PA2 tied to low.
Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.
6.3
Reset Pin
The NRST pin is bidirectional with an open drain output buffer. It is handled by the on-chip reset
controller and can be driven low to provide a reset signal to the external components or asserted
low externally to reset the microcontroller. There is no constraint on the length of the reset pulse,
and the reset controller can guarantee a minimum pulse length. This allows connection of a sim-
ple push-button on the NRST pin as system user reset, and the use of the signal NRST to reset
all the components of the system.
The NRST pin integrates a permanent pull-up resistor to VDDIO
.
6.4
ERASE Pin
The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a
permanent pull-down resistor of about 15 k
Ω to GND.
To eliminate any risk of erasing the Flash due to noise on the ERASE pin, it should be tied exter-
nally to GND, which prevents erasing the Flash from the application, or pulled down with an
external low-value resistor (such as 1 k
Ω).
This pin is debounced by the RC oscillator to improve the glitch tolerance. When the pin is tied to
high during less than 100 ms, ERASE pin is not taken into account. The pin must be tied high
during more than 220 ms to perform the re-initialization of the Flash.
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