參數(shù)資料
型號(hào): AT91F40816-33CI
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: ARM Thumb Microcontrollers
中文描述: 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PBGA120
封裝: BGA-120
文件頁數(shù): 9/22頁
文件大?。?/td> 248K
代理商: AT91F40816-33CI
9
AT91F40816
1348D–ATARM–03/04
Product Overview
Power Supply
The AT91F40816 has a single type of power supply pin, VDD. The VDD pin supplies the
I/O pads and the core. The supported voltage range on V
DD
is 2.7V to 3.6V.
Input/Output
Considerations
The AT91F40816 I/O pads are 5V-tolerant except for the EBI Data Bus (D0 - D15). This
enables the PIO pads to interface with external 5V devices without any additional
components.
After the reset, the microcontroller peripheral I/Os are initialized as inputs to provide the
user with maximum flexibility. It is recommended that in any application phase, the
inputs to the microcontroller be held at valid logic levels to minimize the power
consumption.
Master Clock
The AT91F40816 has a fully static design and works on the Master Clock (MCK), pro-
vided on the MCKI pin from an external source.
The Master Clock is also provided as an output of the device on the pin MCKO, which is
multiplexed with a general-purpose I/O line. While NRST is active, MCKO remains low.
After the reset, the MCKO is valid and outputs an image of the MCK signal. The PIO
Controller must be programmed to use this pin as standard I/O line.
Reset
Reset restores the default states of the user interface registers (defined in the user inter-
face of each peripheral), and forces the ARM7TDMI to perform the next instruction fetch
from address zero. Except for the program counter the ARM7TDMI registers do not
have defined reset states.
NRST Pin
NRST is active low-level input. It is asserted asynchronously, but exit from reset is syn-
chronized internally to the MCK. The signal presented on MCKI must be active within
the specification for a minimum of 10 clock cycles up to the rising edge of NRST, to
ensure correct operation.
The first processor fetch occurs 80 clock cycles after the rising edge of NRST.
Watchdog Reset
The watchdog can be programmed to generate an internal reset. In this case, the reset
has the same effect as the NRST pin assertion, but the pins BMS and NTRI are not
sampled. Boot mode and Tri-state mode are not updated. If the NRST pin is asserted
and the watchdog triggers the internal reset, the NRST pin has priority.
Emulation Functions
Tri-state Mode
The AT91F40816 provides a Tri-state mode, which is used for debug purposes in order
to connect an emulator probe to an application board. In Tri-state mode, all the output
pin drivers of the microcontroller are disabled.
This feature can also be used to program the embedded Flash within a standard NVM
programmer.
To enter Tri-state mode, the pin NTRI must be held low during the last 10 clock cycles
before the rising edge of NRST.
For normal operation, the pin NTRI must be held high during reset, by a resistor of up to
400K Ohm. NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line
TXD1.
相關(guān)PDF資料
PDF描述
AT91FR40161 ARM Thumb Microcontrollers
AT91FR40161-CI ARM Thumb Microcontrollers
AT91FR40162-CI AT91 ARM Thumb Microcontrollers
AT91FR40162 AT91 ARM Thumb Microcontrollers
AT91FR4042 AT91 ARM Thumb Microcontrollers
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