參數(shù)資料
型號: AT90USB647-MU
廠商: Atmel
文件頁數(shù): 25/106頁
文件大?。?/td> 0K
描述: IC AVR MCU 64K 64QFN
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 1,300
系列: AVR®
應(yīng)用: USB 微控制器
核心處理器: AVR
程序存儲器類型: 閃存(64 kB)
控制器系列: AT90 USB
RAM 容量: 4K x 8
接口: 2 線串行,SPI 串行,USART,USB
輸入/輸出數(shù): 48
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
包裝: 托盤
供應(yīng)商設(shè)備封裝: 64-VQFN(9x9)
配用: ATSTK600-TQFP64-ND - STK600 SOCKET/ADAPTER 64-TQFP
ATSTK525-ND - KIT STARTER FOR AT90USB
AT90USBKEY2-ND - KIT DEMO FOR AT90USB
其它名稱: AT90USB647-16MU
AT90USB647-16MU-ND
Q4939729A
25
7593L–AVR–09/12
AT90USB64/128
6.3.2
EEARH and EEARL – The EEPROM Address Register
Bits 15..12 – Res: Reserved bits
These bits are reserved bits in the Atmel AT90USB64/128 and will always read as zero.
Bits 11..0 – EEAR8..0: EEPROM address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 4K
bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096.
The initial value of EEAR is undefined. A proper value must be written before the EEPROM may
be accessed.
6.3.3
EEDR – The EEPROM Data Register
Bits 7..0 – EEDR7.0: EEPROM data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
6.3.4
EECR – The EEPROM Control Register
Bits 7..6 – Res: Reserved bits
These bits are reserved bits in the AT90USB64/128 and will always read as zero.
Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode bits
The EEPROM Programming Mode bit setting defines which programming action that will be trig-
gered when writing EEPE. It is possible to program data in one atomic operation (erase the old
value and program the new value) or to split the Erase and Write operations in two different
operations. The Programming times for the different modes are shown in Table 6-2 on page 26.
While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be
reset to 0b00 unless the EEPROM is busy programming.
Bit
151413
1211
10
9
8
––––
EEAR11
EEAR10
EEAR9
EEAR8
EEARH
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
EEARL
7654
3
2
1
0
Read/write
RRRR
R/W
Initial value
0000
X
XXXX
X
Bit
7654
32
10
MSB
LSB
EEDR
Read/write
R/W
Initial value
0000
00
Bit
7654
32
10
EEPM1
EEPM0
EERIE
EEMPE
EEPE
EERE
EECR
Read/write
R
R/W
Initial value
0
X
0
X
0
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