參數(shù)資料
型號(hào): AT90USB1287-MU
廠商: Atmel
文件頁數(shù): 36/106頁
文件大?。?/td> 0K
描述: IC AVR MCU 128K 64QFN
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
megaAVR Introduction
標(biāo)準(zhǔn)包裝: 1,300
系列: AVR® 90USB
核心處理器: AVR
芯體尺寸: 8-位
速度: 16MHz
連通性: EBI/EMI,I²C,SPI,UART/USART,USB,USB OTG
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 48
程序存儲(chǔ)器容量: 128KB(128K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-VFQFN 裸露焊盤
包裝: 托盤
產(chǎn)品目錄頁面: 611 (CN2011-ZH PDF)
配用: ATSTK600-TQFP64-ND - STK600 SOCKET/ADAPTER 64-TQFP
ATSTK525-ND - KIT STARTER FOR AT90USB
AT90USBKEY2-ND - KIT DEMO FOR AT90USB
其它名稱: AT90USB1287-16MU
AT90USB1287-16MU-ND
35
7593L–AVR–09/12
AT90USB64/128
Figure 6-9.
External data memory cycles with SRWn1 = 1 and SRWn0 = 1
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
SRW00 (lower sector).
The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal
or external).
6.5.6
XMCRA – External Memory Control Register A
Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8,
ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin
direction settings in the respective data direction registers. Writing SRE to zero, disables the
External Memory Interface and the normal pin and data direction settings are used.
Bit 6..4 – SRL2:0: Wait-state Sector Limit
It is possible to configure different wait-states for different External Memory addresses. The
external memory address space can be divided in two sectors that have separate wait-state bits.
The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table 6-4 on page 36 and
Figure 6-4 on page 31. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire
external memory address space is treated as one sector. When the entire SRAM address space
is configured as one sector, the wait-states are configured by the SRW11 and SRW10 bits.
ALE
T1
T2
T3
Wr
ite
Re
a
d
WR
T7
A15:8
Address
Prev. addr.
DA7:0
Address
Data
Prev. data
XX
RD
DA7:0 (XMBK = 0)
Data
Prev. data
Address
Data
Prev. data
Address
DA7:0 (XMBK = 1)
System clock (CLK CPU)
T4
T5
T6
Bit
7654
32
1
0
SRE
SRL2
SRL1
SRL0
SRW11
SRW10
SRW01
SRW00
XMCRA
Read/write
R/W
Initial value
0000
00
0
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