參數(shù)資料
型號: AT90USB1287-16AUR
廠商: Atmel
文件頁數(shù): 82/106頁
文件大?。?/td> 0K
描述: IC MCU AVR 128K ISP USB TQFP64
產(chǎn)品培訓模塊: megaAVR Introduction
標準包裝: 1,000
系列: AVR® 90USB
核心處理器: AVR
芯體尺寸: 8-位
速度: 16MHz
連通性: EBI/EMI,I²C,SPI,UART/USART,USB,USB OTG
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 48
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 4K x 8
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-LQFP
包裝: 帶卷 (TR)
配用: ATSTK600-ND - DEV KIT FOR AVR/AVR32
ATSTK525-ND - KIT STARTER FOR AT90USB
AT90USBKEY2-ND - KIT DEMO FOR AT90USB
77
7593L–AVR–09/12
AT90USB64/128
Table 11-2 summarizes the function of the overriding signals. The pin and port indexes from Fig-
ure 11-5 on page 76 are not shown in the succeeding tables. The overriding signals are
generated internally in the modules having the alternate function.
The following subsections shortly describe the alternate functions for each port, and relate the
overriding signals to the alternate function. Refer to the alternate function description for further
details.
Table 11-2.
Generic description of overriding signals for alternate functions.
Signal name
Full name
Description
PUOE
Pull-up Override
Enable
If this signal is set, the pull-up enable is controlled by the
PUOV signal. If this signal is cleared, the pull-up is
enabled when {DDxn, PORTxn, PUD} = 0b010.
PUOV
Pull-up Override
Value
If PUOE is set, the pull-up is enabled/disabled when
PUOV is set/cleared, regardless of the setting of the
DDxn, PORTxn, and PUD Register bits.
DDOE
Data Direction
Override Enable
If this signal is set, the Output Driver Enable is controlled
by the DDOV signal. If this signal is cleared, the Output
driver is enabled by the DDxn Register bit.
DDOV
Data Direction
Override Value
If DDOE is set, the Output Driver is enabled/disabled
when DDOV is set/cleared, regardless of the setting of
the DDxn Register bit.
PVOE
Port Value
Override Enable
If this signal is set and the Output Driver is enabled, the
port value is controlled by the PVOV signal. If PVOE is
cleared, and the Output Driver is enabled, the port Value
is controlled by the PORTxn Register bit.
PVOV
Port Value
Override Value
If PVOE is set, the port value is set to PVOV, regardless
of the setting of the PORTxn Register bit.
PTOE
Port Toggle
Override Enable
If PTOE is set, the PORTxn Register bit is inverted.
DIEOE
Digital Input
Enable Override
Enable
If this bit is set, the Digital Input Enable is controlled by
the DIEOV signal. If this signal is cleared, the Digital Input
Enable is determined by MCU state (Normal mode, sleep
mode).
DIEOV
Digital Input
Enable Override
Value
If DIEOE is set, the Digital Input is enabled/disabled when
DIEOV is set/cleared, regardless of the MCU state
(Normal mode, sleep mode).
DI
Digital Input
This is the Digital Input to alternate functions. In the
figure, the signal is connected to the output of the schmitt
trigger but before the synchronizer. Unless the Digital
Input is used as a clock source, the module with the
alternate function will use its own synchronizer.
AIO
Analog
Input/Output
This is the Analog Input/output to/from alternate
functions. The signal is connected directly to the pad, and
can be used bi-directionally.
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