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參數(shù)資料
| 型號： | AT90SC6404R |
| 英文描述： | AT90SC6404R Preliminary Summary [Updated 1/03. 4 Pages] |
| 中文描述： | AT90SC6404R初步摘要[更新1 / 03。 4頁] |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 641K |
| 代理商： | AT90SC6404R |
AT90S/LS4434 and AT90S/LS8535
6
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D-
converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following
those of the register file, $20 - $5F.
The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program
memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched
from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is
in-system downloadable Flash memory.
With the relative jump and call instructions, the whole 2K/4K address space is directly accessed. Most AVR instructions
have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effec-
tively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the
usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are exe-
cuted). The 9/10-bit stack pointer SP is read/write accessible in the I/O space.
The 256/512 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
Figure 3.
Memory Maps
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the pro-
gram memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the
interrupt vector address, the higher the priority.
32 Gen. Purpose
Working Registers
64 I/O Registers
Internal SRAM
(256/512 x 8)
$0000
$001F
$0020
$005F
$0060
$015F/$025F
$000
$7FF/$FFF
Data Memory
Program Memory
Program Flash
(2K/4K x 16)
EEPROM
(256/512 x 8)
$000
$0FF/$1FF
Data Memory
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| AT90SC6432R | AT90SC6432R Summary [Updated 11/02. 2 Pages] This document gives the key features. a brief description and a block diagram. The Complete is available under Non-Disclosure Agreement. |
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| AT90SC9616RC | AT90SC9616RC Preliminary Summary [Updated 1/03. 4 Pages] This document gives the key features. a brief description and a block diagram. The Complete is available under Non-Disclosure Agreement. |
| AT90SC9636R | AT90SC9636R Summary [Updated 06/03. 3 Pages] Summary of the AT90SC9636R giving the key features. a brief description and a block diagram. |
| AT91FR4081-40CI | Microcontroller |
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參數(shù)描述 |
|---|---|
| AT90SC6404RFT | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Secure Microcontroller for Smart Cards |
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| AT90SC6404RT_05 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Secure Microcontroller for Smart Cards |
| AT90SC6408RFT | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Secure Microcontrollers for Smart Cards |
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