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參數(shù)資料
| 型號： | AT90L2323-4SI |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 286K |
| 代理商： | AT90L2323-4SI |
7
AT90S2323/LS2323 and AT90S2343/LS2343
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register
operations are also executed in the ALU. Figure 5 shows the AT90S2323/2343 AVR RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.
This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing
them to be accessed as though they were ordinary memory locations.
The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters,
A/D converters and other I/O functions. The I/O memory can be accessed directly or as the Data Space locations following
those of the register file, $20 - $5F.
The AVR has Harvard architecture
–
with separate memories and buses for program and data. The program memory is
accessed with a two-stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the
program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system
downloadable Flash memory.
With the relative jump and call instructions, the whole 1K address space is directly accessed. Most AVR instructions have a
single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the stack. The stack is effec-
tively allocated in the general data SRAM and consequently, the stack size is only limited by the total SRAM size and the
usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are
executed). The 8-bit stack pointer (SP) is read/write-accessible in the I/O space.
The 128 bytes data SRAM + register file and I/O registers can be easily accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
Figure 6.
Memory Maps
EEPROM
(128 x 8)
$000
$07F
EEPROM Data Memory
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT90L2343-4PC | Microcontroller |
| AT90L2343-4PI | Microcontroller |
| AT90L2343-4SC | Microcontroller |
| AT90L2343-4SI | Microcontroller |
| AT90L4433 | AT90S/L4433 Complete [Updated 4/03. 126 Pages] |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT90L2343-4PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| AT90L2343-4PI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| AT90L2343-4SC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| AT90L2343-4SI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| AT90L4433 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AT90S/L4433 Complete [Updated 4/03. 126 Pages] |
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