參數(shù)資料
型號(hào): AT89LP52-20AU
廠商: Atmel
文件頁數(shù): 103/117頁
文件大?。?/td> 0K
描述: IC MCU 8051 8K FLASH SPI 44TQFP
標(biāo)準(zhǔn)包裝: 160
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
86
3709D–MICRO–12/11
AT89LP51/52
implements mode 2 and also blocks reads from the code and data memories; however, reads of
the User Signature Array, Atmel Signature Array, and User Configuration Fuses are still allowed.
The Lock Bits will not disable FDATA or IAP programming initiated by the application software.
17.7
User Configuration Fuses
The AT89LP51/52 includes 10 user fuses for configuration of the device. Each fuse is accessed
at a separate address in the User Fuse Row as listed in Table 17-5. Fuses are cleared by pro-
gramming 00h to their locations. Programming FFh to a fuse location will cause that fuse to
maintain its previous state. To set a fuse (set to FFh) the fuse row must be erased and then
reprogrammed using the Fuse Write with Auto-erase command. The default state for all fuses is
FFh except for Tristate Ports, which defaults to 00h.
Table 17-4.
Lock Bit Protection Modes
Program Lock Bits (by address)
Mode
00h
01h
02h
Protection Mode
1
FFh
No program lock features
200h
FFh
Further programming of the Flash is disabled
300h
00h
FFh
Further programming of the Flash is disabled and verify (read) is also disabled
4
00h
Further programming of the Flash is disabled and verify (read) is also disabled;
External execution above 4K/8K is disabled
Table 17-5.
User Configuration Fuse Definitions
Address
Fuse Name
Description
00 – 01h
Clock Source – CS[0:1](2)
Selects source for the system clock:
CS1
CS0
Selected Source
FFh
High Speed Crystal Oscillator (XTAL)
FFh
00h
Low Speed Crystal Oscillator (XTAL)
00h
FFh
External Clock on XTAL1 (XCLK)
00h
Internal Auxiliary Oscillator (IRC)
02 – 03h
Start-up Time – SUT[0:1]
Selects time-out delay for the POR/BOD/PWD wake-up period:
SUT1
SUT0
Selected Time-out
00h
1 ms (XTAL); 16 s (XCLK/IRC)
00h
FFh
2 ms (XTAL); 512 s (XCLK/IRC)
FFh
00h
4 ms (XTAL); 1 ms (XCLK/IRC)
FFh
16 ms (XTAL); 4 ms (XCLK/IRC)
04h
Compatibility Mode
FFh: CPU functions in 12-clock Compatibility mode
00h: CPU functions is single-cycle Fast mode
05h
ISP Enable(3)
FFh: In-System Programming Enabled
00h: In-System Programming Disabled (Enabled at POR only)
06H
User Signature Programming
FFh: Programming of User Signature Disabled
00h: Programming of User Signature Enabled
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