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    • 參數(shù)資料
      型號(hào): AT89C55WD-24AU
      廠商: Atmel
      文件頁數(shù): 21/34頁
      文件大?。?/td> 0K
      描述: IC 8051 MCU FLASH 20K 44TQFP
      產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
      標(biāo)準(zhǔn)包裝: 160
      系列: 89C
      核心處理器: 8051
      芯體尺寸: 8-位
      速度: 24MHz
      連通性: UART/USART
      外圍設(shè)備: WDT
      輸入/輸出數(shù): 32
      程序存儲(chǔ)器容量: 20KB(20K x 8)
      程序存儲(chǔ)器類型: 閃存
      RAM 容量: 256 x 8
      電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
      振蕩器型: 內(nèi)部
      工作溫度: -40°C ~ 85°C
      封裝/外殼: 44-TQFP
      包裝: 托盤
      PIC10F200/202/204/206
      DS41239D-page 26
      2007 Microchip Technology Inc.
      TABLE 5-2:
      SUMMARY OF PORT REGISTERS
      5.4
      I/O Programming Considerations
      5.4.1
      BIDIRECTIONAL I/O PORTS
      Some instructions operate internally as read followed
      by write operations. The BCF and BSF instructions, for
      example, read the entire port into the CPU, execute the
      bit operation and rewrite the result. Caution must be
      used when these instructions are applied to a port
      where one or more pins are used as input/outputs. For
      example, a BSF operation on bit 2 of GPIO will cause
      all eight bits of GPIO to be read into the CPU, bit 2 to
      be set and the GPIO value to be written to the output
      latches. If another bit of GPIO is used as a bidirectional
      I/O pin (say bit 0), and it is defined as an input at this
      time, the input signal present on the pin itself would be
      read into the CPU and rewritten to the data latch of this
      particular pin, overwriting the previous content. As long
      as the pin stays in the Input mode, no problem occurs.
      However, if bit 0 is switched into Output mode later on,
      the content of the data latch may now be unknown.
      Example 5-1 shows the effect of two sequential
      Read-Modify-Write instructions (e.g., BCF, BSF, etc.)
      on an I/O port.
      A pin actively outputting a high or a low should not be
      driven from external devices at the same time in order
      to change the level on this pin (“wired OR”, “wired
      AND”). The resulting high output currents may damage
      the chip.
      EXAMPLE 5-1:
      READ-MODIFY-WRITE
      INSTRUCTIONS ON AN
      I/O PORT
      5.4.2
      SUCCESSIVE OPERATIONS ON
      I/O PORTS
      The actual write to an I/O port happens at the end of an
      instruction cycle, whereas for reading, the data must be
      valid at the beginning of the instruction cycle (Figure 5-2).
      Therefore, care must be exercised if a write followed by
      a read operation is carried out on the same I/O port. The
      sequence of instructions should allow the pin voltage to
      stabilize (load dependent) before the next instruction
      causes that file to be read into the CPU. Otherwise, the
      previous state of that pin may be read into the CPU rather
      than the new state. When in doubt, it is better to separate
      these instructions with a NOP or another instruction not
      accessing this I/O port.
      Address
      Name
      Bit 7
      Bit 6
      Bit 5
      Bit 4
      Bit 3
      Bit 2
      Bit 1
      Bit 0
      Value on
      Power-On
      Reset
      Value on
      All Other Resets
      N/A
      TRISGPIO
      I/O Control Register
      ---- 1111
      N/A
      OPTION
      GPWU
      GPPU
      T0CS
      T0SE
      PSA
      PS2
      PS1
      PS0
      1111 1111
      03h
      STATUS
      GPWUF
      CWUF
      TO
      PD
      Z
      DC
      C
      00-1 1xxx
      qq-q quuu(1), (2)
      06h
      GPIO
      GP3
      GP2
      GP1
      GP0
      ---- xxxx
      ---- uuuu
      Legend:
      Shaded cells are not used by PORT registers, read as ‘0’, – = unimplemented, read as ‘0’, x = unknown, u =
      unchanged,
      q
      = depends on condition.
      Note 1:
      If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
      2:
      If Reset was due to wake-up on comparator change, then bit 6 = 1. All other Resets will cause bit 6 = 0.
      ;Initial GPIO Settings
      ;GPIO<3:2> Inputs
      ;GPIO<1:0> Outputs
      ;
      GPIO latch
      GPIO pins
      ;
      ----------
      BCF
      GPIO,
      1 ;---- pp01
      ---- pp11
      BCF
      GPIO,
      0 ;---- pp10
      ---- pp11
      MOVLW 007h;
      TRIS
      GPIO
      ;---- pp10
      ---- pp11
      ;
      Note 1:
      The user may have expected the pin val-
      ues to be ---- pp00. The 2nd BCF caused
      GP1 to be latched as the pin value (High).
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