參數(shù)資料
型號: AT89C51RC
廠商: Atmel Corp.
英文描述: 8-bit Microcontroller with 32K Bytes Flash(帶32k字節(jié)閃速存儲器、8位微控制器)
中文描述: 8位32K字節(jié)閃存(帶32K的字節(jié)閃速存儲器,微控制器8位微控制器)
文件頁數(shù): 1/29頁
文件大小: 340K
代理商: AT89C51RC
1
1-megabit
2.7-volt Only
Serial
DataFlash
AT45DB011B
Features
100% Compatible with AT45DB011
Single 2.7V - 3.6V Supply
Serial Interface Architecture
Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 512 Pages (264 Bytes/Page) Main Memory
Optional Page and Block Erase Operations
One 264-byte SRAM Data Buffer
Internal Program and Control Timer
Continuous Read Capability through Entire Array
Fast Page Program Time – 7 ms Typical
120 μs Typical Page to Buffer Transfer Time
Low Power Dissipation
– 4 mA Active Read Current Typical
– 2 μA CMOS Standby Current Typical
20 MHz Max Clock Frequency
Hardware Data Protection Feature
Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3
CMOS and TTL Compatible Inputs and Outputs
Commercial and Industrial Temperature Ranges
Description
The AT45DB011B is a 2.7-volt only, serial interface Flash memory suitable for
in-system reprogramming. Its 1,081,344 bits of memory are organized as 512 pages
of 264 bytes each. In addition to the main memory, the AT45DB011B also contains
one SRAM data buffer of 264 bytes. Unlike conventional Flash memories that are
accessed randomly with multiple address lines and a parallel interface, the DataFlash
uses a serial interface to sequentially access its data. The simple serial interface facil-
itates hardware layout, increases system reliability, minimizes switching noise, and
reduces package size and active pin count. The device is optimized for use in many
Rev. 1984B–09/01
AT45DB011B
Preliminary 16-
Megabit 2.7-volt
Only Serial
DataFlash
(continued)
Pin Configurations
Pin Name
Function
CS
Chip Select
SCK
Serial Clock
SI
Serial Input
SO
Serial Output
WP
Hardware Page
Write Protect Pin
RESET
Chip Reset
RDY/BUSY
Ready/Busy
CBGA Top View
through Package
A
B
C
1
2
3
VCC
WP
RESET
GND
RDY/BSY
SI
SCK
CS
SO
TSSOP Top View
Type 1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
RDY/BUSY
RESET
WP
VCC
GND
SCK
SO
CS
NC
NC
NC
NC
NC
SI
SOIC
1
2
3
4
8
7
6
5
SI
SCK
RESET
CS
SO
GND
VCC
WP
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