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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AT89C51ID2-RLTIM
寤犲晢锛� Atmel
鏂囦欢闋佹暩(sh霉)锛� 71/157闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC 8051 MCU FLASH 64K 44VQFP
妯欐簴鍖呰锛� 160
绯诲垪锛� 89C
鏍稿績铏曠悊鍣細 8051
鑺珨灏哄锛� 8-浣�
閫熷害锛� 60MHz
閫ｉ€氭€э細 I²C锛孲PI锛孶ART/USART
澶栧湇瑷倷锛� POR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 34
绋嬪簭瀛樺劜鍣ㄥ閲忥細 64KB锛�64K x 8锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 2K x 8
RAM 瀹归噺锛� 2K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 5.5 V
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 44-LQFP
鍖呰锛� 鎵樼洡
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20
AT89C51ID2
4289C鈥�8051鈥�11/05
鈥揊
CLK CPU and FCLK PERIPH, for CKRL鈮�0xFF
In X2 Mode:
In X1 Mode:
Timer 0: Clock Inputs
Figure 1. Timer 0: Clock Inputs
Note:
The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock.
SCLKT0 = 0: Timer 0 uses the standard T0 pin as clock input (Standard mode)
SCLKT0 = 1: Timer 0 uses the special Sub Clock as clock input, this feature can be use
as periodic interrupt for time clock.
F
CPU
F
=
CLKPERIPH
F
OSCA
2255
CKRL
鈥�
()
脳
----------------------------------------------
=
F
CPU
F
=
CLKPERIPH
F
OSCA
4255
CKRL
鈥�
()
脳
----------------------------------------------
=
SCLKT0
1
0
FCLK PERIPH
:6
T0 pin
C/T
1
0
OSCCON
TMOD
Gate
INT0
TR0
Timer 0
Control
Sub Clock
(AT 8xC51Ix2 only)
鐩搁棞PDF璩囨枡
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