參數(shù)資料
型號: AT89C51IC2-SLRUL
廠商: Atmel
文件頁數(shù): 118/140頁
文件大?。?/td> 0K
描述: IC 8051 MCU 32K FLASH 44-PLCC
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 500
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 標(biāo)準(zhǔn)包裝
配用: AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU
其它名稱: AT89C51IC2-SLRULDKR
79
AT89C51IC2
4301D–8051–02/08
Reset Value = 00X0 XXXXb
Not Bit addressable
Serial Peripheral DATa Register
(SPDAT)
The Serial Peripheral Data Register (Table 60) is a read/write buffer for the receive data
register. A write to SPDAT places data directly into the shift register. No transmit buffer is
available in this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content
of the shift register.
Table 60. SPDAT Register
SPDAT - Serial Peripheral Data Register (0C5H)
Reset Value = Indeterminate
R7:R0: Receive data bits
SPCON, SPSTA and SPDAT registers may be read and written at any time while there
is no on-going exchange. However, special care should be taken when writing to them
while a transmission is on-going:
Do not change SPR2, SPR1 and SPR0
Do not change CPHA and CPOL
Do not change MSTR
Clearing SPEN would immediately disable the peripheral
Writing to the SPDAT will cause an overflow.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Bit
Number
Bit
Mnemonic Description
7
6
5
4
3
2
1
0
R7
R6
R5
R4
R3
R2
R1
R0
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