參數(shù)資料
型號: AT89C51CC01CA-RLTUM
廠商: Atmel
文件頁數(shù): 22/123頁
文件大?。?/td> 0K
描述: IC 8051 MCU 32K FLASH 44-VQFP
產品培訓模塊: MCU Product Line Introduction
標準包裝: 800
系列: AT89C CAN
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據轉換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 托盤
產品目錄頁面: 616 (CN2011-ZH PDF)
配用: AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU
PIC18F2XK20/4XK20
DS41303G-page 118
2010 Microchip Technology Inc.
9.8
RCON Register
The RCON register contains flag bits which are used to
determine the cause of the last Reset or wake-up from
Idle or Sleep modes. RCON also contains the IPEN bit
which enables interrupt priorities.
The operation of the SBOREN bit and the Reset flag
bits is discussed in more detail in Section 4.1 “RCON
REGISTER 9-10:
RCON: RESET CONTROL REGISTER
R/W-0
R/W-1
U-0
R/W-1
R-1
R/W-0
IPEN
SBOREN(1)
—RI
TO
PD
POR(1)
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IPEN: Interrupt Priority Enable bit
1
= Enable priority levels on interrupts
0
= Disable priority levels on interrupts (Mid-Range Compatibility mode)
bit 6
SBOREN: Software BOR Enable bit(1)
For details of bit operation, see Register 4-1.
bit 5
Unimplemented: Read as ‘0’
bit 4
RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-1.
bit 3
TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-1.
bit 2
PD: Power-down Detection Flag bit
For details of bit operation, see Register 4-1
bit 1
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-1.
bit 0
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-1.
Note 1: Actual Reset values are determined by device configuration and the nature of the device Reset.
See Register 4-1 for additional information.
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