V
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AT89C2051-24SI
寤犲晢锛� Atmel
鏂囦欢闋佹暩(sh霉)锛� 5/19闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� MICRO CONTROLLER
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 38
绯诲垪锛� 89C
鏍稿績铏曠悊鍣細 8051
鑺珨灏哄锛� 8-浣�
閫熷害锛� 24MHz
閫ｉ€氭€э細 UART/USART
澶栧湇瑷�(sh猫)鍌欙細 LED
杓稿叆/杓稿嚭鏁�(sh霉)锛� 15
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 2KB锛�2K x 8锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 128 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4 V ~ 6 V
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 20-SOIC锛�0.295"锛�7.50mm 瀵級
鍖呰锛� 绠′欢
鍏跺畠鍚嶇ū锛� Q1036833A
13
0368H鈥揗ICRO鈥�6/08
AT89C2051
18. External Clock Drive Waveforms
()
19. External Clock Drive
Symbol
Parameter
VCC = 2.7V to 6.0V
VCC = 4.0V to 6.0V
Units
Min
Max
Min
Max
1/t
CLCL
Oscillator Frequency
0
12
0
24
MHz
tCLCL
Clock Period
83.3
41.6
ns
tCHCX
High Time
30
15
ns
t
CLCX
Low Time
30
15
ns
tCLCH
Rise Time
20
ns
t
CHCL
Fall Time
20
ns
20. Serial Port Timing: Shift Register Mode Test Conditions
V
CC = 5.0V 卤 20%; Load Capacitance = 80 pF
Symbol
Parameter
12 MHz Osc
Variable Oscillator
Units
Min
Max
Min
Max
tXLXL
Serial Port Clock Cycle Time
1.0
12 tCLCL
s
t
QVXH
Output Data Setup to Clock Rising Edge
700
10 t
CLCL-133
ns
t
XHQX
Output Data Hold after Clock Rising Edge
50
2 t
CLCL-117
ns
tXHDX
Input Data Hold after Clock Rising Edge
0
ns
t
XHDV
Clock Rising Edge to Input Data Valid
700
10 t
CLCL-133
ns
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
AT90S8515-8JC IC MCU 8K FLSH 8MHZ 44PLCC
PIC24FV16KA304-I/PT MCU 16KB FLASH 2KB RAM 44-TQFP
AT90S8515-8AC IC MCU 8K FLSH 8MHZ 44TQFP
PIC24FJ64GA002-E/SO IC PIC MCU FLASH 64K 28-SOIC
PIC16LF628-04I/SS IC MCU FLASH 2KX14 COMP 20SSOP
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
AT89C2051-24SJ 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU Microcontroller RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
AT89C2051-24SU 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 20 PINS UART 2K FLASH-24MHZ 4-5.5V RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
AT89C2051-24SU SL383 鍒堕€犲晢:Atmel Corporation 鍔熻兘鎻忚堪:MCU 8-bit AT89 80C51 CISC 2KB Flash 5V 20-Pin SOIC T/R
AT89C2051-W-7 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU Microcontroller RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
AT89C2051X2 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:AT89C2051x2 Preliminary [Updated 12/02. 21 Pages]
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�

閲囪臣闇€姹�

(鑻ュ彧閲囪臣涓€姊濆瀷铏�(h脿o)锛屽～瀵竴琛屽嵆鍙�)

鐧�(f膩)甯冩垚鍔�锛佹偍鍙互绻肩簩(x霉)鐧�(f膩)甯冮噰璩笺€備篃鍙互閫�(j矛n)鍏ユ垜鐨勫悗鑷�(t谩i)锛屾煡鐪嬪牨(b脿o)鍍�(ji脿)

鐧�(f膩)甯冩垚鍔燂紒鎮ㄥ彲浠ョ辜绾�(x霉)鐧�(f膩)甯冮噰璩�銆備篃鍙互閫�(j矛n)鍏ユ垜鐨勫悗鑷�(t谩i)锛屾煡鐪嬪牨(b脿o)鍍�(ji脿)

*鍨嬭櫉(h脿o) *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉(h脿o) 灏佽
娣诲姞鏇村閲囪臣

鎴戠殑鑱�(li谩n)绯绘柟寮�

*
*
*
    • 鎴�
    • 閲囪喘
    • 鎼滅储
    • 浼氬憳