TWI Interface AC Timing; V
參數(shù)資料
型號(hào): AT87251G2D-3CSUM
廠商: Atmel
文件頁(yè)數(shù): 50/77頁(yè)
文件大?。?/td> 0K
描述: IC 8051 MCU 32K OTP 24MHZ 40DIP
標(biāo)準(zhǔn)包裝: 216
系列: 8x251
核心處理器: C251
芯體尺寸: 8/16-位
速度: 24MHz
連通性: EBI/EMI,I²C,Microwire,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類(lèi)型: OTP
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
54
AT/TSC8x251G2D
4135F–8051–11/06
AC Characteristics - SSLC: TWI Interface
Timings
Table 47.
TWI Interface AC Timing; VDD = 2.7 to 5.5 V, TA = -40 to 85°C
Notes: 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of
100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-up
resistor, this must be < 1
μs.
3. Spikes on the SDA and SCL lines with a duration of less than 3TCLCL will be filtered
out. Maximum capacitance on bus-lines SDA and
SCL = 400 pF.
4. TCLCL = TOSC = one oscillator clock period.
Waveforms
Figure 18.
TWI Waveforms
Symbol
Parameter
INPUT
Min
Max
OUTPUT
Min
Max
THD; STA
Start condition hold time
14TCLCL(4)
4.0
μs(1)
TLOW
SCL low time
16TCLCL(4)
4.7
μs(1)
THIGH
SCL high time
14TCLCL(4)
4.0
μs(1)
TRC
SCL rise time
1
μs-(2)
TFC
SCL fall time
0.3
μs0.3 μs(3)
TSU; DAT1
Data set-up time
250 ns
20TCLCL(4)- TRD
TSU; DAT2
SDA set-up time (before repeated START
condition)
250 ns
1
μs(1)
TSU; DAT3
SDA set-up time (before STOP condition)
250 ns
8TCLCL(4)
THD; DAT
Data hold time
0 ns
8TCLCL(4) - TFC
TSU; STA
Repeated START set-up time
14TCLCL(4)
4.7
μs(1)
TSU; STO
STOP condition set-up time
14TCLCL(4)
4.0
μs(1)
TBUF
Bus free time
14TCLCL(4)
4.7
μs(1)
TRD
SDA rise time
1
μs
-(2)
TFD
SDA fall time
0.3
μs0.3 μs(3)
TSU;STA
TSU;DAT2
THD;STA
THIGH
TLOW
SDA
(INPUT/OUTPUT)
0.3 VDD
0.7 V
DD
TBUF
TSU;STO
0.7 VDD
0.3 V
DD
TRD
TFD
TRC
TFC
SCL
(INPUT/OUTPUT)
TSU;DAT1
THD;DAT
TSU;DAT3
START or Repeated START condition
START condition
STOP condition
Repeated START condition
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