參數(shù)資料
型號: AT80C51RD2-SLRUM
廠商: Atmel
文件頁數(shù): 2/81頁
文件大?。?/td> 0K
描述: IC MCU 80C51 HI PERFORM 44PLCC
產(chǎn)品培訓模塊: MCU Product Line Introduction
標準包裝: 1
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器類型: ROMless
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 標準包裝
其它名稱: AT80C51RD2-SLRUMDKR
10
4113D–8051–01/09
AT80C51RD2
Figure 6-2.
Mode Switching Waveforms
The X2 bit in the CKCON0 register (see Table 6-1) allows to switch from 12 clock periods per
instruction to 6 clock periods and vice versa. At reset, the speed is set according to X2 bit of
Hardware Config Byte (HCB). By default, Standard mode is activated. Setting the X2 bit acti-
vates the X2 feature (X2 mode).
The T0X2, T1X2, T2X2, UARTX2, PCAX2 and WDX2 bits in the CKCON0 register (Table 6-1)
allow to switch from standard peripheral speed (12 clock periods per peripheral clock cycle) to
fast peripheral speed (6 clock periods per peripheral clock cycle). These bits are active only in
X2 mode.
Table 6-1.
CKCON0 Register
CKCON0 - Clock Control Register (8Fh)
XTAL1:2
CPU Block
X2 Bit
X2 Mode
STD Mode
F
OSC
XTAL1
765
4321
0
-
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
Bit
Number
Bit
Mnemonic
Description
7-
Reserved
Do not set this bit.
6WDX2
Watchdog clock (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
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