參數(shù)資料
型號(hào)： AT80251G2D-SLSUM
廠商： Atmel
文件頁(yè)數(shù)： 76/77頁(yè)
文件大?。?/td> 0K
描述： IC 8051 MCU ROMLESS 44PLCC
標(biāo)準(zhǔn)包裝： 972
系列： 8x251
核心處理器： C251
芯體尺寸： 8/16-位
速度： 24MHz
連通性： EBI/EMI，I²C，Microwire，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器類型： ROMless
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
8
AT/TSC8x251G2D
4135F–8051–11/06
NMI
I
Non Maskable Interrupt
Holding this pin high for 24 oscillator periods triggers an interrupt.
When using the Product Name as a pin-for-pin replacement for a 8xC51
product, NMI can be unconnected without loss of compatibility or power
consumption increase (on-chip pull-down).
Not available on DIP package.
–
P0.0:7
I/O
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. To avoid
any paraitic current consumption, Floating P0 inputs must be polarized to
VDD or VSS.
AD7:0
P1.0:7
I/O
Port 1
P1 is an 8-bit bidirectional I/O port with internal pull-ups. P1 provides
interrupt capability for a keyboard interface.
–
P2.0:7
I/O
Port 2
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
A15:8
P3.0:7
I/O
Port 3
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
–
PROG#
I
Programming Pulse input
The programming pulse is applied to this input for programming the on-chip
EPROM/OTPROM.
–
PSEN#
O
Program Store Enable/Read signal output
PSEN# is asserted for a memory address range that depends on bits RD0
and RD1 in UCONFIG0 byte (see ).
–
RD#
O
Read or 17th Address Bit (A16)
Read signal output to external data memory depending on the values of
bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 20).
P3.7
RST
I
Reset input to the chip
Holding this pin high for 64 oscillator periods while the oscillator is running
resets the device. The Port pins are driven to their reset conditions when a
voltage greater than VIH1 is applied, whether or not the oscillator is running.
This pin has an internal pull-down resistor which allows the device to be
reset by connecting a capacitor between this pin and VDD.
Asserting RST when the chip is in Idle mode or Power-Down mode returns
the chip to normal operation.
–
RXD
I/O
Receive Serial Data
RXD sends and receives data in serial I/O mode 0 and receives data in
serial I/O modes 1, 2 and 3.
P3.0
SCL
I/O
TWI Serial Clock
When TWI controller is in master mode, SCL outputs the serial clock to
slave peripherals. When TWI controller is in slave mode, SCL receives
clock from the master controller.
P1.6
SCK
I/O
SPI Serial Clock
When SPI is in master mode, SCK outputs clock to the slave peripheral.
When SPI is in slave mode, SCK receives clock from the master controller.
P1.6
SDA
I/O
TWI Serial Data
SDA is the bidirectional TWI data line.
P1.7
SS#
I
SPI Slave Select Input
When in Slave mode, SS# enables the slave mode.
P1.4
Table 2.
Product Name Signal Description (Continued)
Signal
Name
Type
Description
Alternate
Function
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