
60
AT/TSC8x251G2D
4135F–8051–11/06
Figure 24.
EPROM Verifying Waveforms
AC Characteristics - External Clock Drive and Logic Level References
Definition of Symbols
Table 53.
External Clock Timing Symbol Definitions
Timings
Table 54.
External Clock AC Timings; VDD = 4.5 to 5.5 V, TA = -40 to +85°C
Waveforms
Figure 25.
External Clock Waveform
Notes: 1. During AC testing, all inputs are driven at VDD -0.5 V for a logic 1 and 0.45 V for a
logic 0.
2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for
a logic 0.
TEHQZ
TELQV
T
AVQV
T
AXQX
P1 = A15:8
P3 = A7:0
P2 = D7:0
P0
Address
Mode = 28h, 29h or 2Bh
Data
Signals
Conditions
C
Clock
H
High
L
Low
X
No Longer Valid
Symbol
Parameter
Min
Max
Unit
FOSC
Oscillator Frequency
24
MHz
TCHCX
High Time
10
ns
TCLCX
Low Time
10
ns
TCLCH
Rise Time
3
ns
TCHCL
Fall Time
3
ns
0.45 V
T
CLCL
VDD - 0.5
V
IH1
V
IL
T
CHCX
T
CLCH
T
CHCL
T
CLCX