參數(shù)資料
型號(hào)： AT49LH00B4-33TC
廠商： ATMEL CORP
元件分類： DRAM
英文描述： 4-megabit Top Boot, Bottom Partitioned Firmware Hub and Low-Pin Count Flash Memory
中文描述： 512K X 8 FLASH 3V PROM, 11 ns, PDSO40
封裝： 10 X 20 MM, PLASTIC, MO-142CD, TSOP1-40
文件頁數(shù)： 1/36頁
文件大?。?/td> 322K
代理商： AT49LH00B4-33TC
1
3379B–FLASH–9/03
Features
Complies with Intel
Low-Pin Count (LPC) Interface Specification Revision 1.1
– Supports both Firmware Hub (FWH) and LPC Memory Read and Write Cycles
Auto-detection of FWH and LPC Memory Cycles
– Can Be Used as FWH for Intel 8xx, E7xxx, and E8xxx Series Chipsets
– Can Be Used as LPC Flash for Non-Intel Chipsets
Top Boot with Bottom Partitioned Memory Array for Efficient Vital Data Storage
– 64-Kbyte Top Boot Sector, Six 64-Kbyte Sectors, One 32-Kbyte Sector, One
16-Kbyte Sector, Two 8-Kbyte Sectors
– Or Memory Array Can Be Divided Into Eight Uniform 64-Kbyte Sectors for Erasing
Two Configurable Interfaces
– FWH/LPC Interface for In-System Operation
– Address/Address Multiplexed (A/A Mux) Interface for Programming during
Manufacturing
FWH/LPC Interface
– Operates with the 33 MHz PCI Bus Clock
– 5-signal Communication Interface Supporting Byte Reads and Writes
– Two Hardware Write Protect Pins: TBL for Top Boot Sector and WP for All
Other Sectors
– Five General-purpose Input (GPI) Pins for System Design Flexibility
– Identification (ID) Pins for Multiple Device Selection
– Sector Locking Registers for Individual Sector Read and Write Protection
A/A Mux Interface
– 11-pin Multiplexed Address and 8-pin Data Interface
– Facilitates Fast In-System or Out-of-System Programming
Single Voltage Operation
– 3.0V to 3.6V Supply Voltage for Read and Write Operations
Industry-Standard Package Options
– 32-lead PLCC
– 40-lead TSOP
Description
The AT49LH00B4 is a Flash memory device designed for use in PC and notebook
BIOS applications. The device complies with version 1.1 of Intel’s LPC Interface Spec-
ification, providing support for both FWH and LPC memory read and write cycles. The
device can also automatically detect the memory cycle type to allow the AT49LH00B4
to be used as a FWH with Intel chipsets or as an LPC Flash with non-Intel chipsets.
4-megabit
Top Boot,
Bottom
Partitioned
Firmware Hub
and Low-Pin
Count Flash
Memory
AT49LH00B4
Pin Configurations
PLCC
Note:
[ ] Designates A/A Mux Interface.
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
[A7] GPI1
[A6] GPI0
[A5] WP
[A4] TBL
[A3] ID3
[A2] ID2
[A1] ID1
[A0] ID0
[I/O0] FWH0/LAD0
IC [IC]
GND
NC
NC
VCC
INIT [OE]
FWH4/LFRAME [WE]
RES [RDY/BSY]
RES [I/O7]
4
3
2
1
3
3
3
1
1
1
1
1
1
2
[
[
G
[
[
[
[
G
G
R
N
V
C
G
TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
[IC] IC
NC
NC
NC
NC
[A10] GPI4
NC
[R/C] CLK
VCC
NC
[RST] RST
NC
NC
[A9] GPI3
[A8] GPI2
[A7] GPI1
[A6] GPI0
[A5] WP
[A4] TBL
GND
VCC
FWH4/LFRAME [WE]
INIT [OE]
RES [RDY/BSY]
RES [I/O7]
RES [I/O6]
RES [I/O5]
RES [I/O4]
VCC
GND
GND
FWH3/LAD3 [I/O3]
FWH2/LAD2 [I/O2]
FWH1/LAD1 [I/O1]
FWH0/LAD0 [I/O0]
ID0 [A0]
ID1 [A1]
ID2 [A2]
ID3 [A3]
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