參數(shù)資料
型號: AT49F1604
廠商: Atmel Corp.
英文描述: 16-megabit 5-volt Only Flash Memory(16M位 5V閃速存儲器)
中文描述: 16兆位5伏只有閃存(1,600位5V的閃速存儲器)
文件頁數(shù): 5/18頁
文件大?。?/td> 337K
代理商: AT49F1604
AT49F1604(T)/1614(T)
5
command is a one-bus cycle command, which does require
the plane address (determined by A18 and A19).
PRODUCT IDENTIFICATION:
The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see
Operating Modes
on page 9 (for hard-
ware operation) or
Software Product Identification
Entry/Exit
on page 14. The manufacturer and device
codes are the same for both modes.
DATA POLLING:
The AT49F16X4(T) features Data Poll-
ing to indicate the end of a program cycle. During a
program cycle an attempted read of the last byte/word
loaded will result in the complement of the loaded data on
I/O7. Once the program cycle has been completed, true
data is valid on all outputs and the next cycle may begin.
During a sector erase operation, an attempt to read the
device will give a
0
on I/O7. Once the program or erase
cycle has completed, true data will be read from the device.
Data Polling may begin at any time during the program
cycle. Please see
Status Bit Table
on page 15 for more
details.
TOGGLE BIT:
In addition to Data Polling, the
AT49F16X4(T) provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
same memory plane will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6
will stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
An additional toggle bit is available on I/O2, which can be
used in conjunction with the toggle bit that is available on
I/O6. While a sector is erase suspended, a read or a pro-
gram operation from the suspended sector will result in the
I/O2 bit toggling. Please see
Status Bit Table
on page 15
for more details.
RDY/BUSY:
An open-drain Ready/Busy output pin pro-
vides another method of detecting the end of a program or
erase operation. RDY/BUSY is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open-drain connection
allows for OR-tying of several devices to the same
RDY/BUSY line.
HARDWARE DATA PROTECTION:
The Hardware Data
Protection feature protects against inadvertent programs to
the AT49F16X4(T) in the following ways: (a) V
CC
sense: if
V
CC
is below 3.8V (typical), the program function is inhib-
ited. (b) V
CC
power-on delay: once V
CC
has reached the
V
CC
sense level, the device will automatically time out
10 ms (typical) before programming. (c) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (d) Noise filter: pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
INPUT LEVELS:
While operating with a 4.5V to 5.5V
power supply, the address inputs and control inputs (OE,
CE and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to V
CC
+ 0.6V.
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