參數(shù)資料
型號(hào)： AT34C02-10PU-2.7
廠商： ATMEL CORP
元件分類(lèi)： PROM
英文描述： 256 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8
封裝： 0.300 INCH, LEAD AND HALOGEN FREE, PLASTIC, MS-001BA, DIP-8
文件頁(yè)數(shù)： 14/20頁(yè)
文件大?。?/td> 295K
代理商： AT34C02-10PU-2.7
3
AT34C02
0958O–SEEPR–12/04
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device
address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other
AT24Cxx devices. When the pins are hardwired, as many as eight 2K devices may be
addressed on a single bus system. (Device addressing is discussed in detail under
“Device Addressing,” page 9.) A device is selected when a corresponding hardware and
software match is true. If these pins are left floating, the A2, A1, and A0 pins will be
internally pulled down to GND. However, due to capacitive coupling that may appear
during customer applications, Atmel recommends always connecting the address pins
to a known state. When using a pull-up resistor, Atmel recommends using 10k
or less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor-
mal write operations. When WP is connected directly to Vcc, all write operations to the
memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down
to GND. However, due to capacitive coupling that may appear during customer applica-
tions, Atmel recommends always connecting the WP pins to a known state. When using
a pull-up resistor, Atmel recommends using 10k
or less.
Note:
1. This parameter is characterized and is not 100% tested.
Table 2. AT34C02 Write Protection Modes
WP Pin Status
Write Protect Register
Part of the Array Write Protected
V
CC
–
Full Array (2K)
GND or Floating
Not Programmed
Normal Read/Write
GND or Floating
Programmed
First-Half of Array
(1K: 00H - 7FH)
Table 3. Pin Capacitance(1)
Applicable over recommended operating range from T
A = 25°C, f = 1.0 MHz, VCC = +1.8V
Symbol
Test Condition
Max
Units
Conditions
CI/O
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
C
IN
Input Capacitance (A
0, A1, A2, SCL)
6
pF
V
IN = 0V
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