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參數(shù)資料
型號: AT32UC3L032-AUT
廠商: Atmel
文件頁數(shù): 150/174頁
文件大?。?/td> 0K
描述: IC MCU 32K FLASH 16K SRAM 48TQFP
產(chǎn)品培訓模塊: MCU Product Line Introduction
AVR® UC3 Introduction
標準包裝: 1,250
系列: AVR®32 UC3 L
核心處理器: AVR
芯體尺寸: 32-位
速度: 50MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 9x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 托盤
配用: ATSTK600-RC34-ND - STK600 ROUTING CARD AVR
其它名稱: 32UC3L032-AUT
32UC3L032-AUT-ND
77
32099I–01/2012
AT32UC3L016/32/64
8.
Flash Controller (FLASHCDW)
Rev: 1.0.2.0
8.1
Features
Controls on-chip flash memory
Supports 0 and 1 wait state bus access
Buffers reducing penalty of wait state in sequential code or loops
Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per
clock cycle for sequential reads
Secure State for supporting FlashVault technology
32-bit HSB interface for reads from flash and writes to page buffer
32-bit PB interface for issuing commands to and configuration of the controller
Flash memory is divided into 16 regions can be individually protected or unprotected
Additional protection of the Boot Loader pages
Supports reads and writes of general-purpose Non Volatile Memory (NVM) bits
Supports reads and writes of additional NVM pages
Supports device protection through a security bit
Dedicated command for chip-erase, first erasing all on-chip volatile memories before erasing
flash and clearing security bit
8.2
Overview
The Flash Controller (FLASHCDW) interfaces the on-chip flash memory with the 32-bit internal
HSB bus. The controller manages the reading, writing, erasing, locking, and unlocking
sequences.
8.3
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
8.3.1
Power Management
If the CPU enters a sleep mode that disables clocks used by the FLASHCDW, the FLASHCDW
will stop functioning and resume operation after the system wakes up from sleep mode.
8.3.2
Clocks
The FLASH CDW has two bus clocks co nn ect e d: O n e High Spe e d Bu s cl ock
(CLK_FLASHCDW_HSB) and one Peripheral Bus clock (CLK_FLASHCDW_PB). These clocks
are generated by the Power Manager. Both clocks are enabled at reset, and can be disabled by
writing to the Power Manager. The user has to ensure that CLK_FLASHCDW_HSB is not turned
off before reading the flash or writing the pagebuffer and that CLK_FLASHCDW_PB is not
turned off before accessing the FLASHCDW configuration and control registers. Failing to do so
may deadlock the bus.
8.3.3
Interrupts
The FLASHCDW interrupt request lines are connected to the interrupt controller. Using the
FLASHCDW interrupts requires the interrupt controller to be programmed first.
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