參數(shù)資料
型號: AT32UC3C2512C-A2ZT
廠商: Atmel
文件頁數(shù): 30/109頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 512KB FLASH 64TQFP
標(biāo)準(zhǔn)包裝: 800
系列: AVR®32 UC3 C
核心處理器: AVR
芯體尺寸: 32-位
速度: 66MHz
連通性: CAN,以太網(wǎng),I²C,IrDA,LIN,SPI,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 45
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 11x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
27
9166DS–AVR-01/12
AT32UC3C
Figure 4-1.
Overview of the AVR32UC CPU
4.3.1
Pipeline Overview
AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc-
tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic
(ALU) section, one multiply (MUL) section, and one load/store (LS) section.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.
Figure 4-2 on page 28 shows an overview of the AVR32UC pipeline stages.
AVR32UC CPU pipeline
Instruction memory controller
MPU
High
Spe
ed
B
u
s
High
Spe
ed
B
u
s
OCD
system
OCD
in
ter
face
Interrupt
co
ntr
olle
r
inter
fa
ce
High
Speed
Bus slave
High
Spe
ed
B
u
s
High Speed Bus master
Power/
Reset
control
Res
et
in
ter
face
CPU Local
Bus
master
CP
U
Lo
cal
Bu
s
Data memory controller
CPU RAM
High Speed
Bus master
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