參數(shù)資料
型號(hào): AT32UC3C1128C-AUT
廠商: Atmel
文件頁數(shù): 3/110頁
文件大小: 0K
描述: IC MCU AVR32 128K FLASH 100TQFP
產(chǎn)品培訓(xùn)模塊: AVR® UC3 Introduction
標(biāo)準(zhǔn)包裝: 450
系列: AVR®32 UC3 C
核心處理器: AVR
芯體尺寸: 32-位
速度: 66MHz
連通性: CAN,以太網(wǎng),I²C,IrDA,LIN,SPI,UART/USART,USB
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 81
程序存儲(chǔ)器容量: 128KB(128K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b,D/A 4x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
包裝: 托盤
配用: ATSTK600-SC03-ND - STK600 TQFP SOCKET CARD AVR
ATSTK600-RC38-ND - STK600 ROUTING CARD AVR
100
32117DS–AVR-01/12
AT32UC3C
Fix/Workaround
None.
3
In host mode, the disconnection during OUT transition is not supported
In USB host mode, a pipe can not work if the previous USB device disconnection has
occurred during a USB transfer.
Fix/Workaround
Reset the USBC (USBCON.USB=0 and =1) after a device disconnection (UHINT.DDISCI).
4
In USB host mode, entering suspend mode can fail
In USB host mode, entering suspend mode can fail when UHCON.SOFE=0 is done just
after a SOF reception (UHINT.HSOFI).
Fix/Workaround
Check that UHNUM.FLENHIGH is below 185 in Full speed and below 21 in Low speed
before clearing UHCON.SOFE.
5
In USB host mode, entering suspend mode for low speed device can fail when the
USB freeze (USBCON.FRZCLK=1) is done just after UHCON.SOFE=0.
Fix/Workaround
When entering suspend mode (UHCON.SOFE is cleared), check that USBFSM.DRDSTATE
is not equal to three before freezing the clock (USBCON.FRZCLK=1).
10.1.11
WDT
1
WDT Control Register does not have synchronization feedback
When writing to the Timeout Prescale Select (PSEL), Time Ban Prescale Select (TBAN),
Enable (EN), or WDT Mode (MODE) fieldss of the WDT Control Register (CTRL), a synchro-
nizer is started to propagate the values to the WDT clcok domain. This synchronization
takes a finite amount of time, but only the status of the synchronization of the EN bit is
reflected back to the user. Writing to the synchronized fields during synchronization can lead
to undefined behavior.
Fix/Workaround
-When writing to the affected fields, the user must ensure a wait corresponding to 2 clock
cycles of both the WDT peripheral bus clock and the selected WDT clock source.
-When doing writes that changes the EN bit, the EN bit can be read back until it reflects the
written value.
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