參數(shù)資料
型號: AT32UC3A4128-C1UR
廠商: Atmel
文件頁數(shù): 16/94頁
文件大?。?/td> 0K
描述: IC MCU 128K FLASH 100VFBGA
產(chǎn)品培訓(xùn)模塊: AVR® UC3 Introduction
標準包裝: 1
系列: AVR®32 UC3 A4
核心處理器: AVR
芯體尺寸: 32-位
速度: 66MHz
連通性: EBI/EMI,I²C,IrDA,MMC,SPI,SSC,UART/USART,USB OTG
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,WDT
輸入/輸出數(shù): 88
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-VFBGA
包裝: 標準包裝
其它名稱: AT32UC3A4128-C1URDKR
23
32072SH–AVR32–10/2012
AT32UC3A3
Figure 4-1.
Overview of the AVR32UC CPU
4.3.1
Pipeline Overview
AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc-
tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic
(ALU) section, one multiply (MUL) section, and one load/store (LS) section.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.
Figure 4-2 on page 24 shows an overview of the AVR32UC pipeline stages.
AVR32UC CPU pipeline
Instruction memory controller
High
Speed
Bus
master
MPU
H
igh
S
pee
d
Bu
s
H
igh
S
pee
d
Bu
s
OCD
system
OC
D
in
te
rfa
ce
In
te
rru
pt
c
on
tro
lle
ri
nte
rfa
ce
High
Speed
Bus slave
H
igh
S
pee
d
Bu
s
Da
ta
RA
M
in
te
rfa
ce
High Speed Bus master
Power/
Reset
control
Re
se
ti
nt
er
fa
ce
CPU Local
Bus
master
CPU
L
oc
al
B
us
Data memory controller
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