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參數(shù)資料
| 型號： | AT28C256-15PC |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | Octal Buffers/Drivers With 3-State Outputs 20-VQFN -40 to 85 |
| 中文描述： | 32K X 8 EEPROM 5V, 150 ns, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, MS-011AB, DIP-28 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 762K |
| 代理商： | AT28C256-15PC |
Device Operation
READ:
The AT28C256 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention in their system.
BYTE WRITE:
A low pulse on the WE or CE input with CE
or WE low (respectively) and OE high initiates a write cy-
cle. The address is latched on the falling edge of CE or
WE, whichever occurs last. The data is latched by the first
rising edge of CE or WE. Once a byte write has been
started it will automatically time itself to completion. Once
a programming operation has been initiated and for the
duration of t
WC
, a read operation will effectively be a poll-
ing operation.
PAGE WRITE:
The page write operation of the AT28C256
allows 1 to 64-bytes of data to be written into the device
during a single internal programming period. A page write
operation is initiated in the same manner as a byte write;
the first byte written can then be followed by 1 to 63 addi-
tional bytes. Each successive byte must be written within
150
μ
s (t
BLC
) of the previous byte. If the t
BLC
limit is ex-
ceeded the AT28C256 will cease accepting data and com-
mence the internal programming operation. All bytes dur-
ing a page write operation must reside on the same page
as defined by the state of the A6 - A14 inputs. For each
WE high to low transition during the page write operation,
A6 - A14 must be the same.
The A0 to A5 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any
order and may be altered within the same load period.
Only bytes which are specified for writing will be written;
unnecessary cycling of other bytes within the page does
not occur.
DATA POLLING:
The AT28C256 features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be pre-
sented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle
may begin. DATA Polling may begin at anytime during the
write cycle.
TOGGLE BIT:
In addition to DATA Polling the AT28C256
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling be-
tween one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
(continued)
DATA PROTECTION:
If precautions are not taken, inad-
vertent writes may occur during transitions of the host sys-
tem power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.
HARDWARE PROTECTION:
Hardware features protect
against inadvertent writes to the AT28C256 in the follow-
ing ways: (a) V
CC
sense - if V
CC
is below 3.8V (typical) the
write function is inhibited; (b) V
CC
power-on delay - once
V
CC
has reached 3.8V the device will automatically time
out 5 ms (typical) before allowing a write: (c) write inhibit -
holding any one of OE low, CE high or WE high inhibits
write cycles; (d) noise filter - pulses of less than 15 ns (typi-
cal) on the WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION:
A software controlled
data protection feature has been implemented on the
AT28C256. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C256 is
shipped from Atmel with SDP disabled.
SDP is enabled by the host system issuing a series of
three write commands; three specific bytes of data are
written to three specific addresses (refer to Software Data
Protection Algorithm). After writing the 3-byte command
sequence and after t
WC
the entire AT28C256 will be pro-
tected against inadvertent write operations. It should be
noted, that once protected the host may still perform a
byte or page write to the AT28C256. This is done by pre-
ceding the data to be written by the same 3-byte command
sequence used to enable SDP.
Once set, SDP will remain active unless the disable com-
mand sequence is issued. Power transitions do not dis-
able SDP and SDP will protect the AT28C256 during
power-up and power-down conditions. All command se-
quences must conform to the page write timing specifica-
tions. The data in the enable and disable command se-
quences is not written to the device and the memory ad-
dresses used in the sequence may be written with data in
either a byte or page write operation.
After setting SDP, any attempt to write to the device with-
out the 3-byte command sequence will start the internal
write timers. No data will be written to the device; however,
for the duration of t
WC
, read operations will effectively be
polling operations.
AT28C256
2-219
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT28C256-15PI | Octal Buffer/Driver With 3-State Outputs 20-SSOP -40 to 85 |
| AT28C256-15SC | Octal Buffer/Driver With 3-State Outputs 20-SSOP -40 to 85 |
| AT28C256-15SI | Octal Buffer/Driver With 3-State Outputs 20-SSOP -40 to 85 |
| AT28C256-15TC | Octal Buffer/Driver With 3-State Outputs 20-TVSOP -40 to 85 |
| AT28C256-15TI | Octal Buffer/Driver With 3-State Outputs 20-TVSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT28C256-15PI | 功能描述:電可擦除可編程只讀存儲器 256K 11MIL GRIND - 150NS IND TEMP RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| AT28C256-15PU | 功能描述:電可擦除可編程只讀存儲器 256K 32K x 8 150 ns 4.5V-5.5V RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| AT28C256-15PU-ND | 制造商:Omron Electronic Components LLC 功能描述:IC EEPROM 256k 50NS 28DIP |
| AT28C256-15SA | 功能描述:IC EEPROM 256KBIT 150NS 28SOIC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤 |
| AT28C256-15SC | 功能描述:電可擦除可編程只讀存儲器 256K 11MIL GRIND - 150NS COM TEMP RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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