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Features
Serial EEPROM Family for Configuring Altera FLEX
Devices
Simple Interface to SRAM FPGAs
EE Programmable 512K and 1M-bit Serial Memories Designed to Store
Configuration Programs for Field Programmable Gate Arrays (FPGAs)
Cascadable Read Back to Support Additional Configurations or Future
Higher-density Arrays
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in the Space-efficient Surface-mount PLCC Package
In-System Programmable Via 2-wire Bus
Emulation of Atmel’s AT24CXXX Serial EEPROMs
Available in 3.3V
± 10% LV and 5V ± 5% C Versions
System-friendly READY Pin
Description
The AT17C512A/010A and AT17LV512A/010A (high-density AT17A Series) FPGA
Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective con-
figuration memory for programming Altera FLEX
devices. The AT17A Series is
packaged in the popular 20-pin PLCC. The AT17A Series family uses a simple serial-
access procedure to configure one or more FPGA devices. The AT17A Series organi-
zation supplies enough memory to configure one or multiple smaller FPGAs. Using a
feature of the AT17A Series, the user can select the polarity of the reset function by
programming four EEPROM bytes. The AT17A parts generate their own internal clock
and can be used as a system “master” for loading the FPGA devices.
The Atmel devices also support a system-friendly READY pin and a write protect
mechanism. The READY pin is used to simplify system power-up considerations. The
WP1 pin is used to protect part of the Configurator memory during in-system
programming.
The AT17A Series Configurators can be programmed with industry-standard program-
mers, or Atmel’s ATDH2200E Programming Kit.
FPGA
Configuration
EEPROM
Memory
512K and 1M
Altera Pinout
AT17C512A
AT17LV512A
AT17C010A
AT17LV010A
Rev. 0974B–07/99
Pin Configurations
PLCC
4
5
6
7
8
18
17
16
15
14
DCLK
WP1
NC
NC
OE
SER_EN
NC
NC
READY
NC
3
2
1
2
1
9
1
1
1
1
n
G
N
(
N
N
D
N
V
N