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參數(shù)資料
| 型號(hào)： | AT1799S-GRE |
| 廠商： | Aimtron Technology Corp. |
| 英文描述： | 2A Step-Down Voltage Regulator |
| 中文描述： | 第2A降壓穩(wěn)壓器 |
| 文件頁(yè)數(shù)： | 12/14頁(yè) |
| 文件大?。?/td> | 356K |
| 代理商： | AT1799S-GRE |
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AT1799
2A Step-Down Voltage Regulator
discharging of the output capacitor.
In the case of low-ESR electrolytic capacitors, Output ripple voltage drop caused by
the switching current through the ESR of the output capacitor. The output ripple is
estimated as:
R
I
V
×
Impacting frequency stability of the overall control loop, the output capacitance, in
conjunction with the inductor, creates a double pole inside the feedback loop. In
addition the capacitance and the ESR value create a zero. These frequency response
effects together with the internal frequency compensation circuitry of AT1799 modify
the gain and phase shift of the closed loop system.
Compensation
The step-down loop can be compensated by adjusting the external components
connected to the COMP pin. The COMP pin is connected to the output of the internal
trans-conductance error amplifier. The compensation capacitor adjusts the low
frequency gain , and the series resistor value adjusts the high frequency gain. A series
capacitor-resistor combination sets a pole-zero combination to control the
characteristics of the control system. The system has 2 poles and one zero of
importance, 2 poles consist of compensation capacitor and output capacitor. One zero
is produced by the compensation capacitor and the compensation resistor.
If electrolytic capacitor with relatively high ESR is used, the zero due to the
capacitance and ESR of the output capacitor can be compensated by a third pole set
by the compensation resistor and another compensation capacitor connected form
COMP pin to ground.
PCB layout guidelines
Careful printed circuit layout is extremely important to avoid causing parasitical
capacitance and line inductance. The following layout guidelines are recommended to
achieve optimum performance.
Please the buck converter diode and inductor close to the SW pin and no via.
Please ceramic bypass capacitors near the input pin.
Locate all feedback resistive dividers as close to their respective feedback pins as
possible.
Use wide traces and trace length is short as possible.
2F, No.10, Prosperity RD. II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C.
Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW:
http://www.aimtron.com.tw
8/23/2006 REV:1.1 Email:
service@aimtron.com.tw
12
ESR
L
RIPPLE
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