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參數(shù)資料
| 型號(hào)： | ASM6312C |
| 廠商： | Aplus Integrated Circuits Inc. |
| 英文描述： | VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR |
| 中文描述： | 成本很低的語(yǔ)音合成器與4位微處理器 |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大?。?/td> | 581K |
| 代理商： | ASM6312C |
Rev 1.0
1
ASM6312C
–
VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR
1.0 General Description
The
ASM6312C
is very low cost voice synthesizer with 4-bit microprocessor. It has various features
including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog timer(WDT), voice
synthesizer, etc. It consists of 22 instructions in the device. With CMOS technology and halt function
can minimize power dissipation. Its architecture is similar to RISC, with two stages of instruction
pipeline. It allows all instructions to be executed in a single cycle, except for program branches and
data table read instructions (which need two instruction cycles).
1.1 Feature
Single power supply can operate from 2.4V through 5V
Internal Program ROM: 4K x 10-bit
1 sets of 18-bit DPR can access up to 192K x 10 bits data memory space
Data Registers:
96 x 4-bit data RAM (00-1Fh plus 40h-7Fh)
Unbanked special function registers (SFR) range: 20h-3Fh
I/O Ports:
PRA: 4-bit I/O Port A (2Bh)
PRB: 4-bit Output Port B (2Dh)
PRC: 4-bit Input Port C (2Fh)
On-chip clock generator: Resistive Clock Drive
(
RM)
Timer: 1
Timer0: a 9-bit auto-reload timer/counter
Stack: 2-level subroutine nesting
HALT and Release from HALT function to reduce power consumption
Watch Dog Timer (
WDT
)
Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles
Number of instruction: 22
ASM6312C
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