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參數(shù)資料
| 型號(hào)： | ASM5I9350G-32-LT |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | Mechanism, 2-inch, front feed, w/ manual knob, platen detect & cutter (full cut) |
| 中文描述： | 200 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | GREEN, LQFP-32 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 473K |
| 代理商： | ASM5I9350G-32-LT |
July 2005
rev 0.2
ASM5I9350
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
3.3V 1:10 LVCMOS PLL Clock Generator
Features
Output frequency range: 25 MHz to 200 MHz
Input frequency range: 6.25 MHz to 31.25 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
± 2.5% max Output duty cycle variation
Nine Clock outputs: Drive up to 18 clock lines
Two reference clock inputs: Xtal or LVCMOS
150pS max output-output skew
Phase-locked loop (PLL) bypass mode
‘SpreadTrak’
Output enable/disable
Pin-compatible with MPC9350 and CY29350.
Industrial temperature range: –40°C to +85°C
32-pin 1.0mm TQFP & LQFP Packages
Functional Description
The ASM5I9350 is a low-voltage high-performance
200MHz PLL-based clock driver designed for high speed
clock distribution applications.
The ASM5I9350 features Xtal and LVCMOS reference
clock inputs and provides nine outputs partitioned in four
banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO
output by 2 or 4 while the other banks divide by 4 or 8 per
SEL(A:D) settings, see Table 2. These dividers allow
output to input ratios of 16:1, 8:1, 4:1, and 2:1. Each
LVCMOS compatible output can drive 50
series or
parallel
terminated
transmission
lines.
For
series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:18.
The PLL is ensured stable given that the VCO is configured
to run between 200MHz to 500MHz. This allows a wide
range of output frequencies from 25MHz to 200MHz. The
internal VCO is running at multiples of the input reference
clock set by the feedback divider, see Table 1.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
does not apply.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9350 | 3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9350-32-ET | 3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9350-32-LT | 3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9351G-32-ET | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351G-32-LT | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9351 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351G-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351G-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
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