參數(shù)資料
型號(hào): ASM4SSTVF16857-48TT
廠(chǎng)商: ALLIANCE SEMICONDUCTOR CORP
元件分類(lèi): 通用總線(xiàn)功能
英文描述: DDR 14-Bit Registered Buffer
中文描述: SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48
封裝: 0.240 INCH, 0.50 MM PITCH, TSSOP-48
文件頁(yè)數(shù): 8/16頁(yè)
文件大?。?/td> 147K
代理商: ASM4SSTVF16857-48TT
August 2004
ASM4SSTVF16857
rev 2.0
Timing Requirements
DDR 14-Bit Registered Buffer
8 of 16
(Over recommended operating free-air temperature range, unless otherwise noted).
Guaranteed by design. Not 100% production tested.
* this parameter is not necessarily production tested.
V
DDQ
= 2.5V±0.2V
V
DDQ
= 2.6V±0.1V
Unit
Symbol
Parameters
Min
Max
Min
Max
f
CLOCK
Clock frequency
200
270
MHz
t
W
Pulse duration, CK, CKLB high or low
2.5
2.5
ns
t
ACT
*
Differential inputs active time
22
22
ns
t
INACT
*
Differential inputs inactive time
22
22
ns
Setup time, fast slew rate
0.75
0.4
t
S
Setup time, slow slew rate
Data before CLK
, CLKB
0.9
0.6
ns
ns
Hold time, fast slew rate
0.75
0.4
t
h
Hold time, slow slew rate
Data after CLK
, CLKB
0.9
0.6
ns
ns
t
SL
Output slew rate, measurement point at 20% and 80%
1
4
1
4
V/ns
Note:
1. Data inputs must be low for a minimum time of t
ACT
max, after which RESETB is taken high.
2. Data and clock inputs must be held at valid levels (not floating) for a minimum time of tINACTmax after which RESETB is taken low.
3. For data signal input slew rate >=V/ns
4. For data signal input slew rate >=0.5 V/ns and < 1V/ns
5. CLK,CLKB signals input slew rates are >=1V/ns
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ASM4SSTVF16857-48VR 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:DDR 14-Bit Registered Buffer
ASM4SSTVF16857-48VT 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:DDR 14-Bit Registered Buffer
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ASM4SSTVF16859-56QR 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:DDR 13-Bit to 26-Bit Registered Buffer
ASM4SSTVF16859-56QT 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:DDR 13-Bit to 26-Bit Registered Buffer