參數(shù)資料
型號(hào): ASC7611
廠商: Electronic Theatre Controls, Inc.
英文描述: HARDWARE MONITOR WITH INTEGRATED FAN CONTROL
中文描述: 五金顯示器整合了風(fēng)扇控制
文件頁數(shù): 26/40頁
文件大?。?/td> 505K
代理商: ASC7611
P
P
- 26 -
Andigilog, Inc. 2006
www.andigilog.com
October 2006 - 70A05007
aSC7611
Bit
Name
R/W
Default
Description
0
START
R/W
0
When software writes a 1 to this bit, the aSC7611 fan monitoring and PWM
output control functions will use the values set in the fan control limit and
parameter registers (addresses 30-32h and 5Fh through 61h). Before this bit
is set, the aSC7611 will not update the used register values, the default values
will remain in effect. Whenever this bit is set to 0, the aSC7611 fan monitoring
and PWM output control functions use the default fan limits and parameters,
regardless of the current values in the limit and parameter registers
(addresses 30-32h and 5Fh through 61h). The aSC7611 will preserve the
values currently stored in the limit and parameter registers when this bit set or
cleared. This bit is not affected by the state of the Lock bit.
It is expected that all limit and parameter registers will be set by BIOS or
application software prior to setting this bit.
Setting this bit to 1 locks specified limit and parameter registers.
WARNING:
Once this bit is set, limit and parameter registers become read-only and will
remain locked
until the device is powered off
. This register bit becomes
read-only once it is set.
1
LOCK
R/W
0
2
READY
R
0
The aSC7611 sets this bit automatically after the part is fully powered up, has
completed the power-up-reset process, and after all A/D converters are
properly functioning.
3
OVRID
R/W
0
If this bit is set to 1, all PWM outputs will go to 100% duty cycle regardless of
whether or not the lock bit is set. The OVRID bit has precedence over the
disabled mode. Therefore, when OVRID is set the PWM will go to 100% even
if the PWM is in the disabled mode.
4-7
RESERVED
R
0
Reserved
Table 9 READY / LOCK / START / OVRID Settings
Register 30-32h: Current PWM Duty Cycle
Register
Address
Read/
Write
Register Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
30h
R/W
Fan 1 Current
PWM Duty
7
6
5
4
3
2
1
0
FF
31h
R/W
Fan 2 Current
PWM Duty
7
6
5
4
3
2
1
0
FF
32h
R/W
Fan 3 Current
PWM Duty
7
6
5
4
3
2
1
0
FF
The Current PWM Duty registers store the current duty cycle at each PWM output. At initial power-on, the PWM duty cycle
is 100% and thus, when read, this register will return FFh. After the Ready/Lock/Start/Override register Start bit is set, this
register and the PWM signals will be updated based on the algorithm described in the Auto Fan Control Operating Mode
section. When Ready/Lock/Start/Override register Start bit is zero, default value (FFh) is used.
When read, the Current PWM Duty registers return the current PWM duty cycle. These registers are read-only unless the
fan is in manual (test) mode, in which case a write to these registers will directly control the PWM duty cycle for each fan.
The PWM duty cycle is represented as shown in Table 10.
If a 3-wire fan is being used and the option to enable 3-wire tach measurement is selected, the effective PWM duty cycle will
be impacted by this feature. The 3-wire Enable setting will hold the PWM signal high for the period taken to make a
tachometer reading. This period depends on the RPM and various tachometer measurement parameters. Overall impact is
that lower PWM commands will be effectively increased and there may be acoustic effects.
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