
- 22 -
Andigilog, Inc. 2006
www.andigilog.com
August 2006 - 70A05003
aSC7512
RAN[3:0]
Linear Control
Range (
°
C)
1010
20
1011
26.67
1100
1101
32 (default)
40
1110
53.33
1111
80
Table 10 Zone Range Setting, RAN[3:0]
This register becomes Read-Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write
to this register shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override
register Start bit is cleared even though modifications to this register are possible.
Register 40h: Ready/Lock/Start/Override
Register
Address
Read/
Write
Register Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
40h
R/W
Ready/Lock/Start/
Override
RES
RES
RES
RES
OVRID
READY
LOCK
START
00
Bit
Name
R/W
Default
Description
0
START
R/W
0
When software writes a 1 to this bit, the aSC7512 fan monitoring and PWM
output control functions will use the values set in the fan control limit and
parameter registers (address 5Ch through 6Eh). Before this bit is set, the
aSC7512 will not update the used register values, the default values will
remain in effect. Whenever this bit is set to 0, the aSC7512 fan monitoring
and PWM output control functions use the default fan limits and parameters,
regardless of the current values in the limit and parameter registers (5C
through 6E). The aSC7512 will preserve the values currently stored in the
limit and parameter registers when this bit set or cleared. This bit is not
affected by the state of the Lock bit.
It is expected that all limit and parameter registers will be set by BIOS or
application software prior to setting this bit.
Setting this bit to 1 locks specified limit and parameter registers.
WARNING:
Once this bit is set, limit and parameter registers become read-only and will
remain locked
until the device is powered off
. This register bit becomes
read-only once it is set.
1
LOCK
R/W
0
2
READY
R
0
The aSC7512 sets this bit automatically after the part is fully powered up, has
completed the power-up-reset process, and after all A/D converters are
properly functioning.
3
OVRID
R/W
0
If this bit is set to 1, all PWM outputs will go to 100% duty cycle regardless of
whether or not the lock bit is set. The OVRID bit has precedence over the
disabled mode. Therefore, when OVRID is set the PWM will go to 100% even
if the PWM is in the disabled mode.
4-7
RESERVED
R
0
Reserved
Table 11 READY / LOCK / START / OVRID Settings
Register 30h: Current PWM Duty Cycle
Register
Address
Read/
Write
Register Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
30h
R/W
Fan Current PWM
Duty
7
6
5
4
3
2
1
0
N/A